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EDNE DEC 2014

BY Pinkesh Sachdev, Linear Technology Soft management of power system hardware Power system architects and designers of digital ASIC/ FPGA/microprocessor boards may be justified in being a little envious of their colleagues in software engineering if you were to consider the following advantages that the software team has over their hardware colleagues. The time delay between writing software code and observing its effect is much shorter than the days or weeks that a hardware board spin takes. The time to market is mostly limited by their coding and testing productivity and less by extraneous factors. Software updates are pushed to the customer as-needed to fix bugs and improve field performance. Hardware updates require boards to be recalled for rework. Software engineers easily track performance of their code through logged data from the comfort of their cubicles. Performance bottlenecks are quickly identified Figure 1. The DPSM architecture. POL supplies stay analogue with digital communication and control added in. leading to rapid future improvements. On the other floor, hardware engineers spend days in the lab, hunched over boards with voltmeter and oscilloscope probes. Software engineers write one core set of modular code and then adapt it for different customer and market needs. Customised hardware requires component and bill of materials (BOM) changes, risking designs diverging from each other. Increasing challenges facing power system architects & designers Exacerbating the situation, tougher challenges face the power system team on modern digital boards as nanometer-scale processor (ASIC, FPGA, microprocessor, DSP) supply voltages continue their downward march below 1V. The tolerance requirements on point of load (POL) supplies are tightening up, approaching 2% to 3%; the error budget includes DC accuracy, ripple and transient excursions during Figure 2. DPSM device types, each offering multiple devices, depending on the number of supply rails to be controlled. load steps. Note that 3% of a 0.9V supply is just 27 mV. As supply voltages drop and more cores are packed into processors, current levels rise, even exceeding 100A. Maintaining accuracy to a few tens of millivolts at the processor input with one hundred Amperes flowing through the power and ground planes is a daunting PDN (power distribution network) design task. Simultaneously, there is a push for more efficient use of processing energy to lower data centre utility bills and cooling costs. Server chassis are running hotter with board temperatures approaching 100C. Design cycles are getting shorter but designs need to be refined at the last minute depending on margin test results and also for the unique needs of different markets and customers. Sequencing has been a common requirement on boards with multiple supplies, but those requirements are getting more complex as the number of supplies ranges from 20 to 50, spanning multiple power domains. Solutions so far Power management tasks such as sequencing, supervision, monitoring and margining have been handled by an assortment of devices including supervisors, sequencers, ADCs, DACs, amplifiers and microcontrollers. Coordinating these disparate devices to work together takes up most of the design effort. Integrated solutions have generally evolved or descended from supervisors and sequencers with capabilities added for margining, ADC monitoring and EEPROM fault logging. However, these devices have poor voltage accuracy on trimming, margining and monitoring. There are also system-on-chip (SoC) devices that integrate an array of uncommitted digital gates and logic with ADCs, DACs, comparators and PWM outputs. Lacking any power management architecture, these devices require a lot of programming to perform even the most basic tasks, taking up months of design and validation effort. The push towards digital management of power systems has led to digital power solutions where the DC/DC converter loop employs an ADC, digital compensator and digital PWM. Due to the inherent quantisation of this sampled system, digital loops generate more noise and ripple in the supply output voltage. They also tend to have slower transient response, poorer accuracy and, at worst, even erratic, unpredictable behaviour. On the other hand, analogue loops are faster, cleaner and much more predictable. Management of multiple supplies requires digital configuration and communication with the POL supply but the supply loop itself can stay analogue to obtain the best of both the analogue and digital worlds. The complete solution Keeping POL supply trends in mind was a major part of the rationale that lay behind a complete Digital Power System Management (DPSM) solution, architected starting from first principles. The core philosophy is that the supply loops stay analogue, with digital interface and control added in. This is illustrated in Figure 1. The DPSM family includes a broad array of interoperable devices with and without built-in DC/DC conversion, as shown in Figure 2. All of these devices communicate with a board controller via the industry standard PMBus interface. The choice of PMBus helps reduce design time by enabling firmware re-use. For those preferring autonomous operation without the need for code development, an engineering-level development software is provided to customise device configuration. This article concludes with a description of the various digital management block functions; how fault logging becomes available; and the applicability to power environments with many power rails. Complete article, here 16 EDN Europe | DECEMBER 2014 www.edn-europe.com


EDNE DEC 2014
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