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readerS SOLVE DESIGN PROBLEMS designideas Monolithic PWM generator runs fast, minimises silicon Jindrich Windels , Ann Monte & Jan Doutreloigne  In IC design, the typical approach for generating a pulse width-modulated (PWM) signal from an analogue value (such as in the control loop for a switch mode power supply) uses a ramp or triangle wave fed to one input of a comparator, and the analogue control voltage connected to the second input of the comparator. This circuit, shown in Figure 1, is time-tested and can operate at high frequencies, but you need an amplifier and comparator (or two amplifiers) to generate the PWM signal. Alternatively, a pure digital approach is possible, where a freerunning counter is compared with a register value, although the maximum PWM frequency is limited by the need for a clock signal several orders of magnitude over the desired PWM frequency – for acceptable resolution. Figure 1. Analogue PWM circuit using triangle wave generator and comparator In this Design Idea, we show an alternative circuit. It uses very little power, can be implemented in a small silicon area, and can achieve high PWM frequencies. In the design, shown in Figure 2, the PWM signal is generated based on an analogue control voltage and a clock signal at the PWM frequency. The analogue control voltage is used to modulate the capacitive load in a delay line – using a FET as a control element – which alters the delay, and hence the pulse width. This simple yet powerful circuit is extremely compact to integrate on a chip. For example, a 10 MHz version of the circuit, including a driver for a 10 pF capacitive load in the ON Semiconductor C035 0.35 μm technology, can occupy as little as 120 μm × 70 μm. The power consumption of the IC block is low, and mostly dependent on the load. For example, when operating at 3V, power consumption in simulation is approximately 1.057 mW at 10 MHz with a 10 pF load, and 248 μW with a 1 pF load, so most of the energy is used for charging the input of the next stage or the measurement probe. Figure 3. Layout plot of the PWM block. In the actual chip, the block is covered with metal layers for interconnections, so a picture shows little of interest. The circuit was manufactured as part of a larger design through the Europractice Multi-Project Wafer (MPW) service, and the functionality was verified through measurements. In Figure 4, the pulse widths in simulation and measurement are plotted. Unfortunately, the power consumption of the PWM circuit could not be verified experimentally because other circuits use the same power rail. Figure 2. Proposed PWM generator circuit Figure 4. Simulated and measured pulse width for the integrated PWM generator www.edn-europe.com EDN Europe | DECEMBER 2014 19


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