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EDNE MARCH 2013

OUR VIRTUAL PANEL SHARES EYE-OPENING AD VICE FOR ANTI CIPATIN G, DETECTIN G, AND MITIGATING SI PROBLEMS IN FAST ER, IN CREASIN GLY COMPLEX DESIGNS. Electronics design trends that ratchet up design complexity and speed, such as the use of multiple high-speed buses, bring new signal-integrity challenges. With that in mind, EDN assembled a virtual panel of engineers working in signal integrity to examine the current impairments, assess how well the available test equipment is measuring up, and determine what we can do both short- and long-term to improve signal integrity. Admittedly, there are many things that can affect signal integrity (Reference 1); in this discussion, we focus primarily on crosstalk and EMI. What ’s the problem? Many a trained eye is focused on the effects of multiple high-speed buses on signal integrity and how to avoid the related problems. Chris Loberg, senior technical marketing manager at Tektronix Inc, and Tim Caffee, vice president for design validation and test at Asset InterTech Inc, agree that shrinking operating margins on high-speed buses are contributing to the challenges. “The design trend is faster serial speeds, above 10 Gbits/sec, with no new cost-effective architecture for improving signal-path accommodation of issues like EMI and crosstalk,” Loberg observes. “So, signaling accommodations like equalization must be made to minimize EMI and crosstalk effects, enabling the receiver to accurately determine the serial-bus logic transition.” Loberg notes that interval times—the time between a transition to one or zero—are shrinking; as a result, in a traditional eye diagram used to evaluate transitions, EMI and crosstalk are “closing” the eye. Engineers can no longer effectively evaluate signal integrity, as crossing points and timing-integrity evaluations become much more challenging. Caffee notes that with each successive generation of high-speed bus, operating margins are gradually shrinking as signal frequencies increase, enabling effects such as jitter, intersymbol interference (ISI), and crosstalk to “create havoc” on the signal integrity of high-speed SerDes and memory channels. Each new step to a higher speed and signaling frequency makes the bus more susceptible to distortions and anomalies that can effectively disrupt traffic and stall system throughput. w ww.edn-europe.com MARCH 2013 | EDN Europe 17


EDNE MARCH 2013
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