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The eye diagram in Figure 1 illustrates this point, showing the effects of increasing signal frequencies on three generations of a hypothetical high-speed bus and the resultant, decreasing operating margins on the bus. As frequencies increase, even the slightest distortion can disrupt signaling throughput. Alan Blankman, product manager for signal-integrity products at Teledyne LeCroy, agrees that higher bit rates (>25 Gbits/sec) and “parallelized serial” standards such as PCI Express (PCIe), 40/100GBase-R, and InfiniBand are contributing to signal-integrity issues. “Faster bit rates require faster edges with higher-frequency content, which results in bigger reflections due to impedance mismatches at connectors, vias, packages, etc.; higher levels of loss; and higher levels of crosstalk and EMI, due to increased coupling to neighboring traces,” Blankman says. Shamree Howard, signal-integrity program manager at Agilent Tech- nologies, adds that faster speeds create issues for accurate data capture, requiring precise triggering. She says jitter measurements are the key to characterizing high-speed digital links, noting, “The measurement of jitter—even if the user is provided a one-button interface—is a sophisticated affair, taking into account clock recovery and knowledge of phase-locked loops, jitter decomposition techniques and assumptions for them, crosstalk and its effects, and waveform statistics that require different approaches” (Reference 2). Howard adds that the Agilent U4154A 4-Gbit/sec AXIe logic-analyzer module can make reliable measurements on eye AT A GLANCE Each new step to a higher speed and signaling frequency makes the bus more susceptible to distortions and anomalies that can disrupt traffic and stall system throughput. “Parallelized serial” standards are contributing to signal-integrity issues. Circuits at very high speeds are notoriously difficult to probe. One way forward is to improve the signal path itself with an optical backplane; another way to improve signal integrity is to trick the signal using equalization approaches to minimize crosstalk. Many designers are managing crosstalk and EMI through better design practices around the signal path. Most engineers working on signal-integrity issues agree that simulation is becoming mandatory for highspeed system design. openings as small as 100 psec × 100 mV (Figure 2). Howard Johnson of Signal Consulting Inc concurs that circuits at very high speeds are notoriously difficult to probe. “Even in cases when a probe exists that can do the job, you often cannot place the probe at the point in a circuit that you wish to observe,” says Johnson. He suggests that the answer is to use cosimulation, or the process of simultaneously developing both a physical circuit and a software simulation of it. The problem, observes Ransom Stephens of Ransom’s Notes, is that, despite new oscilloscope techniques from leading manufacturers, there is no automated way to identify crosstalk unambiguously. The latest test products offer ways to estimate the effect of crosstalk on the bit error rate (BER), but they are all process-of-elimination approaches. “Avoiding crosstalk is simple in principle but sometimes impossible in practice,” Stephens acknowledges. Because crosstalk is caused by jolts of radiation when an aggressor signal makes a logic transition, increasing the rise/fall times will reduce crosstalk. Because it’s interference, increasing trace separation has a big effect, too. “I think that careful differential design is your best bet, though,” Stephens offers. “If you can get the differential skew really small and get the two traces nearly on top of each other, then the cancellation from differential signaling has a fighting chance.” How do we improve si? According to Tektronix’s Loberg, there are several ways forward. First, change and improve the signal path itself. One way to do that is with an optical backplane; despite new oscilloscope techniques, there is no automated way to identify crostalk unambiguously . this is happening, but not in the mainstream (think Thunderbolt). Another way to improve signal integrity is to trick the signal using equalization approaches to minimize crosstalk; for instance, you could hard-code the chip or compile FPGA code to equalize the signal. In addition, many designers are managing crosstalk and EMI through better design practices around the signal path. Asset InterTech’s Caffee proposes that engineers validate signal integrity on the bus during each of the major phases of a system’s life cycle, from design to field operation, though he recognizes that this is a challenging approach and thus not a popular one. If detected during prototype-board bring-up, signal-integrity problems could trigger changes in the design; if detected during manufacturing, problems could result in alterations to the production process. If problems are detected in the field as a result of troubleshooting poorly perform- VOLTAGE (mV) −100 0 20 40 60 100 −80 −60 −40 −20 80 TIMING (pSEC) 60 40 20 0 −20 −40 −60 Figure 1 Moving from 6 (broken line) to 8 (dotted line) and, eventually, 10 Gbits/sec (solid line) closes the eye around the operational sweet spot at the center of the diagram (courtesy Asset InterTech). 18 EDN Europe | MARCH 2013 www.edn-europe.com


EDNE MARCH 2013
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