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scope with a 13-GHz bandwidth, whereas transmitter testing needs a 20-GHz scope. “Emerging multilane designs like InfiniBand and 40/100GBase-R have even more-demanding requirements for channel count and bandwidth,” Blankman says. “These standards utilize bit rates of 25 and 28 Gbits/sec. Typically, an oscilloscope with four or five times the fundamental frequency is needed, which corresponds to 50 to 65 GHz. Since InfiniBand and 40/100GBase-R are multilane, acquiring eight, 12, or even more channels at a time is required to fully characterize SI issues.” Blankman points to Teledyne LeCroy’s LabMaster 10 Zi, with bandwidth out to 65 GHz and a ChannelSync architecture that synchronizes up to 80 channels to operate as a single instrument. • Network analyzers. Network analyzers are important for characterizing crosstalk in multilane systems and revealing the frequency characteristics of the DUT. Anritsu’s Goto points out that in order to acquire the best S-parameter data, the vector network analyzer should have broad frequency coverage. He suggests Anritsu’s VectorStar VNA, which ranges from 70 kHz to 125 GHz. “While the upper frequency receives most of the attention,” he warns, “it is important to remember that accurate measurements to the lowest possible frequency are critical for signal-integrity applications. Often, the accuracy of models can be improved by measuring down to as close to dc as possible, providing the precise data to help create a high-accuracy eye diagram.” Blankman notes that network analyzers with high port counts can be expensive. He says the network analyzers in Teledyne LeCroy’s SPARQ series (Figure 4) were designed for signal-integrity measurements and offer a lower-cost option to a traditional VNA. (SPARQ stands for “S-parameters quick.”) • Software. Given the need for more simulation, vendors are developing software tools to work with their hardware. Loberg notes the availability of serial-data-link analysis (SDLA) on the Tektronix scope (Figure 5), which can help engineers simulate equalization in EDA environments such as those from Cadence Design Systems or Mentor Graphics. “That software model can be Figure 5 This screen image of serial-data-link analysis shows different eye diagrams before and after inclusion of equalization effects and channel/fixturing effects (courtesy Tektronix). dropped into an oscilloscope, transferring the model properties into the JTAG provides aces to an external software -based platform that can manage the system’s embeded instruments. S-parameters; then we can place the effects of that effort into a filter on the scope,” Loberg explains. “The scope can then model the behavior of the equalizer into the signal being measured and see if we can open the eye. This approach allows you to analyze the performance with the effects of equalization baked into the scope.” Teledyne LeCroy also offers oscilloscope based serial-data-analysis software in its SDAIII-CompleteLinQ product. Blankman notes that it is important to have scope-based software that performs eye, jitter, and vertical noise analysis. He says users also need tool kits that allow fixtures and interconnects to be de-embedded or emulated, and that apply transmitter and receiver equalization. “The analysis tool kit should also provide a wide variety of plots that show the variation and distribution of jitter and noise in frequency and time in order to understand the root causes of noise and jitter,” Blankman adds. • BERT. “Receiver testing is becoming mandatory in many standards, and most people don’t know where to start,” says Howard, who adds that system calibration—critical for ensuring the accuracy of your measurements—may be the hardest part of testing. Howard reveals that in working with engineers, she has found proper calibration of the stress signal in PCIe 3.0 to be challenging. She points to the Agilent N4903B J-BERT high-performance serial BERT to test Rx compliance. The instrument can characterize a receiver’s jitter tolerance and is designed to prove compliance with today’s most popular serialbus standards, including PCIe, SATA/ SAS, DisplayPort, and USB. Goto suggests that when selecting a BERT, engineers should choose one with minimal intrinsic jitter. For example, the Anritsu MP1800A has intrinsic clock jitter of <350 fsec RMS. The BERT should also be able to conduct repeatable and stable jitter-tolerance tests with a variety of generated jitter types, such as sinusoidal, random, and bounded uncorrelated jitter and spread-spectrum clock that can be measured up to 32.1 Gbits/ sec. • Embedded test. The days of probing test pads are coming to a close, especially for high-speed buses, because the practice can introduce anomalies into the signal. So where does w ww.edn-europe.com MARCH 2013 | EDN Europe 21


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