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Figure 3 Scope traces are shown for a cardiac-resynchronization device pacing in a saline tank—a standard test environment for pacemaker validation. ADCVDD DVDD CS SCLK SDI SDO DRDY GPIO0/MCS GPIO1/MSCLK GPIO2/MSDO GPIO3 CLK_IO PACELVLTH PACE PULSE LEADING EDGE LEADING EDGE STOP PACE WIDTH PACEEDGETH RECHARGE PULSE Figure 2 In this example of an ideal pacing artifact, the positive pulse has a fast rising edge. After the pulse reaches its maximum amplitude, a capacitive droop follows, and then the trailing edge occurs. The artifact then changes polarity for the recharge portion of the pacing pulse. REFIN REFOUT CAL_DAC_IO RLD_SJ RLD_OUT CM_IN CM_OUT/WCT SHIELD AVDD IOVDD DRIVEN LEAD AMP 10k VCM_REF (1.3V) BUFFER PACEAMPTH ELECTRODES ×5 EXT RESP_LA EXT RESP LL EXT RESP_RA ADAS1000 ADCVDD, DVDD 1.8V REGULATORS AC LEAD-OFF DETECTION PACE DETECTION FILTERS, CONTROL, AND INTERFACE LOGIC CLOCK GEN/OSC/ EXTERNAL CLK SOURCE XTAL1 XTAL2 SHIELD DRIVE AMP COMMONMODE AMP 5× ECG PATH AMP ADC AMP ADC RESPIRATION PATH VREF CALIBRATION RESPIRATION LEAD-OFF MUXES DAC DAC AC DAC Figure 4 The block diagram shows the ADAS1000 analog front end. w ww.edn-europe.com MARCH 2013 | EDN Europe 31


EDNE MARCH 2013
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