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Figure 2 IC designers are integrating ADCs, DACs, and modulators in the transducers on opposite ends of the signal chain, thereby eliminating the need to route any analog audio signals on the PCB and reducing the number of devices in the signal chain. An example of a completely digital audio signal chain is shown here. alternatively be called BCLK, for “bit clock,” or SCLK, for “serial clock.” The name of an IC’s serial data pin varies most from one IC vendor to another and even among a single vendor’s products. A quick survey of audio IC data sheets shows that the SD signal may also be called SDATA, SDIN, SDOUT, DACDAT, ADCDAT, or other variations on these, depending on whether the data pin is an input or an output. An I2S data stream can carry one or two channels of data with a typical bit-clock rate between 512 kHz, for an 8-kHz sampling rate, and 12.288 MHz, for a 192-kHz sampling rate. The data word length is often 16, 24, or 32 bits. For word lengths less than 32 bits, the frame length is often still 64 bits; the unused bits are just driven low by the transmitting IC. Although it is rare, some ICs support only I2S interfaces with a maximum of 32- or 48-bit clocks per stereo-audio frame. When using such an IC, the system designer must take care to ensure that the devices on the other end of its connections also support those bit-clock rates. Though I2S is the most commonly used format, there are other variants of the same three-wire configuration, such as left-justified, right-justified, and PCM modes. Such formats differ from I2S based on the position of the data word in the frame, the polarity of the clocks, or the number of bit-clock cycles in each frame. TD M f ormats Some ICs support multiple I2S data inputs or outputs using a common clock, but such an approach obviously increases the number of pins necessary to transfer the data. TDM formats are used when more than two channels of data are to be transferred on a single data line. A TDM data stream can carry as many as 16 channels of data and has a data/clock configuration similar to that of I2S. Each channel of data uses a slot on the data bus that is 1/Nth the width of the frame, where N is the number of channels being transferred. For practical purposes, N is usually rounded up to the nearest power of two (2, 4, 8, or 16), and any additional channels are left empty. A TDM frame clock is often implemented as a single bit-wide pulse, as opposed to the 50% duty-cycle clock of I2S. Clock rates above 25 MHz are not commonly used for TDM data, because higher frequencies cause board-layout issues that PCB designers would rather avoid. TDM is commonly used for systems in which multiple sources feed one input or one source drives multiple devices. In the former case (multiple sources feeding one input), each TDM source shares a common data bus. The source must be configured to drive the bus only during its appropriate channel and to tristate its driver when other devices are driving other channels. No standard akin to the Philips standard for I2S exists for TDM interfaces, and as a result many ICs have their own, slightly different flavor of TDM implementation. The variants can differ in such aspects as clock polarity, channel configuration, and tristating or driving unused channels. Of course, the different ICs will usually work together, but the system I2S SOURCE MODULATION AND DECIMATION FILTER I2S RECEIVER (PROCESSOR, CODEC) BIT CLOCK BIT CLOCK FRAME CLOCK FRAME CLOCK GENERATOR SERIAL DATA OUTPUT SERIAL DATA INPUT CLOCK Figure 3 An I2S bus uses three signal lines for data transfer: a frame clock, a bit clock, and a data line. The receiving IC, the transmitting IC, or even a separate clock-master IC can generate the two clocks, depending on the system architecture. w ww.edn-europe.com MARCH 2013 | EDN Europe 35


EDNE MARCH 2013
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