# EDNE MAY 2014

designideas This equation simplifies as: R13 = –36kΩ × (V+ – 2.5 – VEB)/(V+ – 10 – VEB) For the NTE-244, VEB = 1.5 V, so the equation becomes: R13 = 36kΩ × (V+ – 4)/(11.5 – V+) The graph shows the results at five example voltages. The circuit has no problem sinking 5A at lower voltages, or handling 50W to 60W at higher output voltages, subject of course to proper heat sinking and temperature derating of the NTE-244 power device. Note that the circuit regulates far better than a Zener diode while operating over a much higher current range. Simple capacitance meter bins surface-mount parts by Raju Baddi  This Design Idea describes a simple two-chip CMOS circuit that can sort capacitors into 20 bins over a wide range (100 pF to 1 μF), using 10 LEDs to display the value range. The circuit is power efficient and can be run using two CR2032 cells. As such, it can be built into a handheld probe. The heart of the circuit is the RS flip-flop using 4093 NAN D gates along with transistors Q1 and Q2, which discharge the reference and test capacitors respectively. The reference capacitor (CREF) and the test capacitor (CX) are charged from zero volts, followed by a reset pulse applied to the bases of Q1 and Q2. Depending on the values of the capacitors and their respective series resistors, either CX or CREF reaches the gates’ VT before the other; accordingly the outputs of the RS flip-flop are set/reset. The outputs are so wired such that when CREF reaches VT before CX, a clock pulse is applied to the CD4017 counter, whose outputs (Q0-Q9) charge CREF through one of 10 different series resistor values (R0-R9). The master clock that runs the circuit is derived using a single 4093 Schmitt NAN D gate. This steps the 4017 decoded decade counter, the flip-flop “comparing” the voltage ramps across CX and CREF while charging CREF through the different values. When CX reaches VT before CREF, then 4017 is not clocked, and the appropriate LED starts flashing indefinitely. Depress the reset switch to take another reading, which resets the 4017 and selects the minimum resistor value, R0. There are two ranges, each divided into 10 sections, which cover 100 pF-10 nF and 10 nF-1 μF. The range is selected by an SPDT switch which connects a CREF of either 100 pF or 10 nF. A particular flashing LED indicates that the value of the test capacitor lies in the range between it and the next lower LED. Q3 takes care of lighting the LED in the appropriate phase of the master clock. The anodes of the 10 LEDs are connected to the outputs (Q0-Q9) of the CD4017. It seems that lower values of charging resistors can result in more reliable readings due to smaller errors in the charging current (contributed mainly by reverse conduction in all the diodes). R0-R9 can be scaled appropriately, together with an inverse scaling of the master clock frequency. Figure 1. Capacitance meter schematic. A 4011 NAND can exhibit some hysteresis, but a 4093 is recommended. Figure 2. A possible handheld probe construction example using a glue stick tube. www.edn-europe.com EDN Europe | MAY 2014 29

EDNE MAY 2014
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