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EDNE MAY 2014

pulse Altera drops “hard” floating point blocks into FPGAs Altera is claiming a programmable-logic “first” with an announcement that it has implemented IEEE 754-compliant hardened floating-point DSP blocks on FPGAs, and that it is shipping the feature now, in its Arria 10 FPGAs. Among other advantages, designs can be finalised with floating-point DSP without the need to convert to fixed-point. Integrating hardened IEE 754-compliant, floating-point operators in an FPGA provides you with, Altera says, greater levels of DSP performance, designer productivity and logic efficiency. The hardened floating point DSP blocks are integrated in Altera’s 20 nm Arria 10 FPGAs and SoCs – currently shipping – and will be in its 14 nm Stratix 10 FPGAs and SoCs. Integrated hardened floating-point DSP blocks, combined with an advanced high-level tool flow, assist you to use Altera’s FPGAs and SoCs in computationally intensive applications, such as high-performance computing (HPC), radar, scientific and medical imaging. The hardened single-precision floating point DSP blocks included in Arria 10 and Stratix 10 devices are based on Altera’s variable precision DSP architecture. Unlike traditional approaches that implement floating point by using fixed point multipliers and FPGA logic, Altera uses efficient, hardened floating point DSP blocks to eliminate nearly all the logic usage required for existing FPGA floating-point computations. This yields up to 1.5 TeraFLOPs (floating point operations per second) DSP performance in Arria 10 devices and up to 10 TeraFLOPs DSP performance in Stratix 10 devices, the company asserts. DSP designers are able to choose either fixed or floating-point modes and the floating point blocks are backwards compatible with existing designs. FPGAs feature a fine-grained, highly pipelined architecture that make them ideally suited for use as high-performance compute accelerators. The inclusion of hardened floating-point DSP blocks enables designers to use Altera FPGAs to address more complex HPC problems in big data analytics, seismic modelling for oil and gas industries and financial simulations. Across these and other computationally intensive applications, FPGAs deliver the highest performance per Watt when compared to DSPs, CPUs and GPUs, Altera adds. Altera further claims that you can also cut development time by months. Designers can translate their DSP designs directly into floating-point hardware, rather than converting their designs to fixed point. As a result, timing closure and verification times Write “Cooler GUIs” with development editor Altia is a user interface development software company that provides tools for the creation of graphical user interfaces for embedded devices, with users in automotive, medical, industrial, fitness, and home appliance industries. The latest release, Altia Design 11.1, is the centrepiece of Altia’s user interface development tool suite. With the new features are reduced. Altera also provides multiple tool flows that allow hardware designers, model-based designers and software programmers to target the high-performance floating-point DSP blocks in its devices. Altera has also disclosed (story here) early results with the Intel 14-nm TriGate process; test chips it has fabricated in 14 nm finfet – or Tri-Gate, as Intel terms it – confirm expected performance, power and density advantages. Altera built some of its key intellectual property (IP) components – transceivers, mixed-signal IP and digital logic – used in Stratix 10 FPGAs and SoCs, on the test chips: Altera and Intel collaborated on the development of the industry’s first FPGA-based devices exploiting Intel’s process technology and Altera’s programmable logic technology. Intel says it has a “true die shrink” with its second-generation 14 nm Tri-Gate process, relative to alternative FinFET technologies. In Intel’s 14 nm Tri-Gate process and an enhanced highperformance core fabric architecture, Stratix 10 FPGAs and SoCs will target advanced, high performance applications in the communications, military, broadcast and compute and storage markets, while cutting system power. Core operating performance will be up to 1 GHz. For high-performance systems that have the most strict power budgets, Stratix 10 devices allow customers to achieve up to a 70% reduction in power consumption by trading performance for power. Complete article, here rolled into Altia Design 11.1, users are equipped to develop better GUIs than ever before, its writers claim. Altia offers a GUI editor and graphics code generator that enable development teams to build completely custom user interface models with graphics created from scratch or imported from industry-standard design programs such as Adobe Photoshop. The Altia GUI can be connected to a variety of simulation tools or C code to create a complex, user-driven model which can be shared with users and management teams for testing and validation prior to production. Once approved, Altia’s code generator automatically generates pure C source www.edn-europe.com EDN Europe | MAY 2014 7


EDNE MAY 2014
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