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EDNE MAY 2015

BY Bonnie Baker, Texas Instruments BAKER’S BEST Complete the simulation of your ADC with IBIS The easy-to-use successive-approximation analogue-to-digital converters (SARADCs) may not be as easy as you think. In my last article “Simulating the front end of your ADC,” (see the March digital edition of EDN Europe, page 19), we talked about macromodels that allow the simulation of the SARADC analogue interfaces (VIN and REFIN). In the analogue evaluation, the ADC driving amplifier and voltage reference are an integral part of a mixed-signal circuit. In the digital domain, the input/output terminals of the SARADC, connecting digital chips and PCB traces fall into the digital simulation category. Now, let’s go into the digital simulation domain. It is prudent to be concerned about the integrity of the digital interface, which involves a converter input clock, output data stream, and various digital control signals. If you have not looked at your board-level transmission line overshoot, undershoot, or crosstalk problems, it is possible to inadvertently compromise the signal-integrity of the clock or data signals. You can anticipate and troubleshoot these types of problems by using digital simulation tools. The PCB’s digital signal-integrity relies on timing, voltage-current levels, and parasitics. This is where the digital I/O (input/output) buffer information specification (IBIS) model comes into play. IBIS simulation An IBIS simulation provides signal information for an IC device’s digital buffers in relation to the PCB traces and the connected digital gate. The IBIS model contains the device buffer’s parasitic inductance/resistive/capacitive values, DC current-voltage (I-V) data, and AC voltagetime (V-t) tables. These tables can be examined in the ADS8660 IBIS model, which is also the ADS8881 IBIS model. Texas Instruments collects the data for the IBIS model using the product’s SPICE deck, or on the bench. Instead of evaluating precision issues, as can be done with the TINA-TI spice model, use the IBIS model to evaluate digital signal-integrity issues. The digital interface in Figure 1 could be between the SAR-ADC and the digital host. On the PCB, there are traces or transmission lines that connect these two devices. The basic elements of a transmission line are shown in Figure 1. Figure 1 Here is an example of a single-ended transmission-line circuit. (Ref 1) In Figure 1, ZT is the notation for the transmitter’s output resistance, and ZR is the notation for the receiver’s input resistance. These specifications are not available in standard datasheets; however, the IBIS model does supply them. The definition of the transmission line, or PCB trace, includes the characteristic impedance (Z0), propagation delay (D), line propagation delay (tD), and trace length (LENGTH). If very little is matching between ZT, Z0 and ZR, the trace is capable of generating electrical ringing. A typical design includes several transmission lines on the PCB (Figure 2). 23 EDN Europe | MAY 2015 www.edn-europe.com


EDNE MAY 2015
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