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E D A Insights FinFET impact on dynamic power Arvind Narayanan FinFET transistors are now in production at the major foundries, having gone from drawing board to products on the shelf in record time. FinFET adoption has been growing steadily because they deliver better power, performance, and area compared to their planar counterparts. This makes them very compelling for smartphones, tablets, and other products that require long battery life and snappy performance. Figure 1 shows the advantages in speed, power usage, and density of TSMC’s 16nm finFET process over two other processes. When Intel first used finFETs at the 22nm node, they claimed 37% better performance (at the same total power) or 50% power reduction (at the same speed) than bulk, PDSOI, or FDSOI. These numbers are compelling, and continue to improve even down to 14nm, and presumably, beyond. In terms of power usage, controlling power leakage has been a huge challenge for planar devices, especially at smaller nodes. By raising the channel and wrapping the gate around it, finFETs create a fully depleted channel to overcome the leakage problems of planar transistors. The better channel control of finFETs leads to lower threshold and supply voltages. While leakage is under control in finFETs, dynamic power consumption accounts for a significant chunk of the total power. FinFETs have higher pin capacitances compared to planar transistors, which results in higher dynamic power numbers. According to Cavium networks, “FinFETs bring a 66% increase in gate capacitance per micron compared to 28 nm process, and are at the same level as that of the 130-nm planar node.” Figure 2 charts the gate capacitances of planar and finFET devices. So what does this mean to the design engineer and how does it change the IC design flow from an implementation perspective? Dynamic (aka switching) power needs to become a cost function during optimisation and has to be considered at all the stages of the flow. FinFETs add to the complexity of physical design flow. Tighter design rules and finFET process requirements, such as voltage threshold aware spacing, implant layer rules, etc., impose restrictions on synthesis, placement, floorplanning, and optimisation engines that directly impact design metrics. And because finFETs are being implemented at 16/14 nm, multi-patterning automatically becomes a part of any design using finFETs, which adds yet another layer of complexity. Design automation technologies for finFETs need to be finFET-aware to reduce switching power and offer capabilities such as power-aware RTL synthesis, activity-driven placement and optimisation, CTS (clock tree synthesis) power reduction, and concurrent optimisation of both dynamic and leakage. Power optimisation needs to start early in the design flow and the architecture selection needs to be power-friendly to ensure lowest power when the design is realised. Figure 1. FinFET performance, power, and area advantages (Source: TSMC. Presented at Open Innovation Platform 2014) 41 EDN Europe | MAY 2015 www.edn-europe.com


EDNE MAY 2015
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