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E D A Insights Figure 2. FinFET gate capacitance compared to planar processes (Source: Cavium Networks) The digital implementation process starts with RTL synthesis. Since finFETs are used in the newest, largest designs, the RTL synthesis engine must have the capacity to handle 100+ million gates with reasonable runtimes. Of course, it must also deliver high-quality results, which can be achieved by running RTL synthesis at the full-chip level when all aspects of the chip can be taken into account. It also helps to be able to run multiple synthesis jobs with different design constraints to explore design alternatives. Having visibility on how the design metrics affect one another lets you make smart trade-offs to meet power, performance, and area metrics. In order to meet power goals, an implementation flow needs to employ a variety of powerreduction strategies, starting from synthesis and continuing through the physical design flow. The most common strategies include multithreshold libraries, clock gating, muti-corner/ multi-mode (MCMM) power optimisation, pin swapping, register clumping, remapping, and power-density driven placement. RTL-level power analysis is essential to analyse and fix power problems early in the design flow. Ability to cross probe between RTL, and layout will help identify and debug problems early in the design flow and minimise last-minute surprises. As mentioned earlier, power optimisation needs to be done in all stages of the design flow and should be done concurrently with other design metrics, such as performance and area. The optimisation engine should include dynamic power in its costing and employ transforms such as sizing cells, deleting cells or moving cells to reduce switching wire capacitance. Design implementation tools for advanced nodes that utilise finFETs must be enhanced and updated with close cooperation from the various foundries. A lot of engineering partnership goes on between the foundries, EDA companies, and mutual customers so that chip designers can take full advantage of each new process node. FinFETs are already in production and have delivered on the promise of scalability, performance, and leakage power, but have added a lot more complexity to the design implementation flow. Arvind Narayanan is a Product Marketing Manager at Mentor Graphics. He holds a Masters in EE from Mississippi State University and a Masters in Business Administration from Duke University. 42 EDN Europe | MAY 2015 www.edn-europe.com


EDNE MAY 2015
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