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EDNE MAY 2015

pulse Imagination lets universities see source RTL for a “real” MIPS core Imagination Technologies says it is revolutionising education in CPU architectures by introducing a university programme that gives “free and open” access to a modern MIPS CPU; the MIPSfpga programme lets universities study MIPS RTL code and explore a real MIPS CPU. As part of the programme participating university departments can get free and open access to a fully-validated, current generation MIPS CPU in a complete teaching package. CPU architecture is generally taught as part of electronic engineering, computer science and computer engineering courses, and is based one (or more) of a small number of major CPU architectures. Until now, says Imagination, what’s been missing from all of these courses is access to real, unobfuscated RTL code that will enable staff and students to study and explore a real CPU. Through MIPSfpga, Imagination is providing universities with a simplified version of its MIPS microAptiv CPU core which has been configured by an academic specifically for academic use. Many academics are already familiar with the microAptiv CPU, and it already has a broad ecosystem of support based on its use in numerous commercial products including the PIC32MZ microcontroller (MCU) from Microchip Technology. The MIPS CPU is being offered as part of a complete free-todownload package for universities, together with a Getting Started Guide, teaching guide for professors, and examples designed to enable students to see how the CPU works and explore its capabilities. With the materials, students can develop a CPU and take it through debug, running on an FPGA platform. This CPU, the company adds, has all the features (MMU, cache controllers, debug interfaces, etc.) required to run a full blown operating system (e.g. Linux). This is contrast to other university programmes where the core is usually encrypted (i.e. a black box) and can only run a simple RTOS. This MIPS CPU configuration is designed to run on a low-cost FPGA platform, with guides available for the Digilent Nexys4 platform with a Xilinx Artix-7 FPGA, and the Terasic DE2 platform with an Altera Cyclone FPGA. 4Mb serial F-RAM for mission-critical data storage Cypress Semiconductor’s ferroelectric RAM range gains a 4 Mbit serial variant that the company positions as expanding the density range of the most energyefficient nonvolatile RAMs. These serial ferroelectric random access memories (F-RAMs) are, Cypress says, the industry’s highest density serial F-RAMs. The 4Mb serial F-RAMs feature a 40-MHz Serial Peripheral Interface (SPI), a 2.0V to 3.6V operating voltage range and are available in industrystandard, RoHS-compliant package options. All Cypress F-RAMs provide 100-trillion read/write cycle endurance with 10-year data retention at 85°C and 151 years at 65°C. Cypress F-RAMs are suitable for applications requiring continuous and frequent high-speed reading and writing of data with absolute data security. The 4 Mb serial F-RAM family addresses mission- Complete article, here 8 EDN Europe | MAY 2015 www.edn-europe.com


EDNE MAY 2015
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