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Transistor-cost declines slowing, Synopsys says By Rick Merritt Moore’s Law wil continue for the next decade, but declines in cost/transistor won’t be as great as they were in the past, said Synopsys chairman Aart de Geus. Growing complexity of chip designs is delaying a shift to larger wafers and may open doors for alternative technologies, he said at an annual event for Synopsys users. His comments come at a time of increasing concern about the future of semiconductor technology. Some observers say the 28nm node could be the last to deliver the full range of benefits traditional with a new silicon node -- lower costs and power and higher performance. Looking ahead, “the jury is out in how fast price comes down per transistor -- that’s a function of how quickly yields improve,” de Geus told a press gathering here. “It is possible that as the price decrease of transistors lowers, the price of semiconductors has to go up” so chip makers can recoup their investments, he said. de Geus said he contacted Mark Bohr to get the Intel fellow’s views. Bohr said he sees a path to a 7nm node and the “possibility of somehow lowering the price per transistor,” de Geus reported. Analyst G. Dan Hutcheson said little data is available about the cost/ transistor in future nodes. However, he is projecting the industry will continue to see cost declines based on its past history. Starting at 20nm, fabs have to pattern some chip layers twice due to the lack of next-generation lithography tools. But lithography only represents roughly a quarter of the cost of making a chip, Hutcheson said. In the face of potentially higher costs, “people will try to use today’s 28nm node as much as they can,” de Geus said. “Only a few people will move to the 20nm node because its benefits are not that high, so they will wait for 16/14nm nodes,” he added. That could open the door to alternatives such as the fully depleted siliconon insulator technology proposed by STMicroelectronics and others. “But it would take other major players to put their weight behind” FD-SOI for it to take off, he said.Given the increasing costs and complexity of making chips, semiconductor companies have put off a shift from 300 to 450 mm wafers until 2020, he said. Larger wafers can sometimes provide lower costs but they also require “a complete retooling of the industry and that’s not happening right now,” he said. Interestingly, only about five percent of the designs done in Synopsys’ tools are at today’s leading-edge 28nm process, according to one foil in de Geus’s keynote. The 180nm node is the most popular, used by nearly 30% of the designs using its tools, followed by the 65nm and 250nm nodes. Powering your next design. Let us be your power expert. We understand that you don’t have the time to master every aspect of electronic design. As a leading manufacturer of power supplies we are here to collaborate with you to ensure your next project is a success. Dc-Dc Converters www.cui.com/PowerExpert Novum® Advanced Power Ac-Dc Power Supplies www.electronics-eetimes.com Electronic Engineering Times Europe April 2014 19


EETE APR 2014
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