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Smart power switch replaces discretes in powertrain and automotive body electronics Texas Instruments’ smart, high-side power switch has programmable current limit, provides the highest level of current sense, and accurate diagnostics, without calibration. As automotive systems become more complex, the various loads within the system can each require different profiles during operation. Using the TPS1H100-Q1, designers can drive various loads with flexibility in powertrain, body-electronics safety and driver-information systems where reliability is paramount. The TPS1H100-Q1 has a 5-mA current-sense accurac, 20% higher than alternative devices according to TI, it provides adjustable current-limit capability to allow flexible control; and its high-voltage avalanche structure eliminates Zener transient voltage suppressors and free-wheel diodes. The chip is AEC Q100-012 Grade A compliant. An automotive BCM reference design addresses common design challenges such as load driving, condition diagnostics and fault detection. Designers can use this TI Designs reference design to quickly design door locks; window lifts; seat heaters; heating, ventilation and air conditioning (HVAC); lamps; and lightemitting diodes (LEDs). Support comes in the form of the TPS1H100EVM evaluation module (EVM) that allows users to evaluate the TPS1H100-Q1 for resistive, capacitive and inductive load layout. Texas Instruments www.ti.com New 8051 IP core is 29X faster than original IP Core provider Digital Core Design (DCD) has introduced its fastest 8051 MCU IP core to date, the DQ8051, boasting a Dhrystone 2.1 performance rating of 0.27292 DMIPS/MHz, or a 29.01 times speed-up over the original 80C51 chip operating at the same frequency. Not only that, but the DQ8051’s dynamic power consumption can be as low as 1.2μW/MHz. “If our DT8051 is the World’s smallest 8051, then the DQ8051 is the World’s fastest 8051 for sure”, claims Kandora, Vice President at Digital Core Design. “The nearest competition stopped at 26x, with the power consumption almost two times higher than DCD’s”. According to DCD, the DQ8051 Dhrystone score rates at 29.01x the original at the same frequency, with only 7.5k gates while the nearest solution consumes almost 12k gates and achieves not more than a 26x speed improvement. The DQ8051 is available with USB, Ethernet, I2C, SPI, UART, CAN, LIN, HDLC, Smart Card interfaces. It also comes equipped with DoCDTM hardware debugger with unique Instruction Smart Trace technology (IST). IST doesn’t capture addresses of all executed instructions, but only these related to the start of tracing, conditional jumps and interrupts. This method not only saves time but also allows improving the size of the IST buffer and extending the trace history. Captured instructions are read back by DoCD-debug software, analyzed and then presented to the user as ASM code and related C lines. Digital Core Design http://dcd.pl/ipcore/197/dq8051/ PMC module hosts high-density user-programmable FPGA TEWS Technologies (Halstenbek, Germany) has the TPMC634, a standard single-width 33 MHz 32-bit PMC module providing a user programmable FPGA with front-I/O and P14 rear-I/O. The TPMC634 is designed for industrial, COTS, and transportation applications, where specialised I/O or long-term availability is required. The TPMC634 provides a number of advantages including a customizable interface for unique customer applications and a FPGA-based design for long-term product lifecycle management. The TPMC634 I/O interface is pin and function compatible to the now obsolete TPMC630 (appropriate order options are available). The user programmable FPGA is a Xilinx Spartan-6, accessible via an on-board local bus. The TPMC634 user programmable FPGA is typically auto-configured from an on-board SPI Flash device. The SPI Flash is insystem programmable via the PCI bus or via a JTAG header. The user programmable FPGA may also be programmed directly (volatile) via the PCI bus or via the JTAG header. The TPMC634-10R provides 64 ESD-protected TTL lines using TTL compatible buffers. The TPMC634-11R provides 32 differential I/O lines using ESD-protected EIA-422 / EIA-485 compatible line transceivers. TEWS Technologies www.tews.com Software brings PAM-4 analysis capability to Keysight oscilloscopes A new software option for Keysight Technologies’ S-Series, V-Series and Z-Series real-time oscilloscopes enables users to chararacterise PAM-4 (pulse amplitude modulation with four amplitude levels) signals. Mobile computing applications are demanding more of the underlying computer Internet infrastructure. To enable higher Internet and serverfarm performance, higher-speed connectivity among server systems is required. Conventional communication techniques often relied upon NRZ (non-return-to-zero) encoding. Industry experts however contend NRZ will not work in a 56-Gbit/s environment. One way to overcome this challenge is to change the modulation technique from NRZ to pulse amplitude modulation. This allows engineers to dramatically increase the amount of data they can send across high-speed digital communication links. Several industry standards bodies are actively promoting PAM-4 technology to enable the next-generation speed class and push higher data rates for a given channel compared to traditional NRZ signaling. While PAM-4 technology leverages some traditional NRZ measurement algorithms for PAM-4 signals, to fully analyze system performance, unique PAM-4 measurements and parameters are required. N8827A/B PAM-4 analysis software offers measurements such as: eye width, eye height and eye skew; level amplitude, level noise and level skew; as well as amplitude level linearity. Keysight Technologies www.keysight.com www.electronics-eetimes.com Electronic Engineering Times Europe April 2015 41


EETE APR 2015
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