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MIPI DSI Host and peripheral IP cores 4-MB Flash memory device in 65nm and 40nm rated at -55 to +210ºC HDL Design House has released the MIPI DSI Host (HIP 3500) and Texas Instruments has unveiled the SM28VLT32-HT, a high- Peripheral (HIP 3510) IP cores, fully compliant with the MIPI Alli- temperature, nonvolatile Flash memory device specifically ance DSI specification. Part of the company’s FlexIP core library, designed for harsh environments, with an operational capac- these DSI IP solutions can be used in tandem with HDL Design ity of 4MB. The chip eliminates the House MIPI D-PHY IP core, available in advanced technology need for costly up-screening and nodes and with silicon proven status. The MIPI DSI Host IP core qualification testing of industrial- (HIP 3500) is a configurable digital core, compliant with the MIPI grade components for temperature Alliance DSI specification, providing a high-speed serial interface ranges outside data sheet specifi- between an application processor and MIPI DSI compliant display. cations. The device allows data logging at extreme tempera- It supports MIPI DSI protocol version 1.1, MIPI DCS version 1.0, tures and is guaranteed for at least 1,000 hours of operating MIPI DBI version 2.0, MIPI DPI version 2.0, MIPI D-PHY version life in harsh environment applications, including oil and gas 1.0. The HIP 3500 is fully compliant with AMBA AHB Version 2.0 exploration, heavy industrial, and avionics. The nonvolatile Compliant Slave Interface. HDL Design House HIP 3500 can be Flash memory device is qualified to work in temperatures configured to handle 1 to 4 data lanes and supports image resolu- ranging from -55 to +210ºC and is tested across the entire tions: QQVGA, QVGA, VGA, WVGA, XVGA, Full-HD and pixel temperature range to provide robust read/write operation formats: RGB 16, 18, 24 bits (a.k.a. RGB565, RGB666, RGB888). over the device’s operating life. The chip is available in either The MIPI DSI Periph (Device) IP core (HIP 3510) receives pixel data a 8x25mm ceramic flat pack or in Known Good Die (KGD) for and commands from host processor through D-PHY interface and small package integration into multi-chip modules. sends data to DPI or DBI interfaces. HIP 3510 is a highly configu- Texas Instruments rable digital IP core, supporting 1 to 4 data lanes. The HIP 3510 www.ti.com is fully compliant to MIPI Alliance’s DSI, MIPI DBI version 2.0, DPI version 2.0, and DCS standards, as well as to AMBA’s AHB speci- fication. HDL Design House HIP 3500 can be configured to handle Clock IC integrates the crystal, frequency 1 to 4 data lanes and supports image resolutions: QQVGA, QVGA, VGA, WVGA, XVGA, Full-HD and pixel formats: RGB 16, 18, 24 synthesizer and fan-out buffer bits, (a.k.a. RGB565, RGB666, RGB888). Micrel’s ClockWorks Fusion family of clock generation products HDL Design House is the first to integrate the crystal, frequency synthesizer and www.hdl-dh.com fan-out buffer in a 5x7mm LGA package, claims the company. The first product in the series, the MX85 is aimed at simultane- Stress-relieved high voltage X7R MLCC ously meeting the ultra-low jitter (less than 200fs) and integra- tion requirements of 10/40/100 Gigabit Ethernet, PCIe 2.0/3.0, delivers 4x improvement in capacitance Fibre Channel, SAS/SATA, and high speed reference clock- The StackiCap X7R devices from Syfer dramatically increase ing for FPGA and SerDes applications. Integrating the crystal the maximum capacitance values now possible in larger case delivers a complete clocking solution in a compact package sizes and high voltages, which significantly reduces printed that eliminates the design burden imposed by existing discrete circuit board real estate. The solutions. With jitter performance that accounts for fan-out buf- company uses a patent-pending fers, this custom configurable (OTP) clocking solution reduces technique to produce a single customers’ bill-of-material (BOM) and footprint, simplifies PCB multilayer chip which reduces design, and enhances overall system performance. The MX85 electro-mechanical stresses in the can be configured up to five outputs of two different frequencies body of the component, whereby supporting LVPECL, LVDS, HCSL and CMOS logic types. a proprietary layer decouples Micrel mechanical stress across thick www.micrel.com devices. This allows for consistent and reliable performance of thicker and larger size devices. The first parts to become available in the StackiCap family will be 1812 and 2220 case sizes, with 200V to 1.5kV and 200 to 2kV operating voltage ranges respectively. Claiming an industry first, Syfer’s 2220 500V device features 1µF capacitance in a single chip. The 2kV part also features an impressive 100nF capacitance pre- viously found only in the much larger case sizes. Meanwhile, in the 1812 range, the 200V part also features 1µF capaci- tance, while the 1kV device features 180nF capacitance, previously only possible in larger size components. In some instances, the parts will allow for a size reduction from 8060 to 2220, providing a factor of 10 saving in board space. This range is fully compliant with the RoHS and is available now on a standard 6 week delivery for production volumes. Syfer Technology www.syfer.com www.electronics-eetimes.com Electronic Engineering Times Europe December 2012 47


EETE DECEMBER 2012
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