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said Rowen. “It has a CoreSight compatible interface for performance monitoring so that fits nicely with the memory.” This adds multi-core on-chip debug with break-in/ break-out and works closely with Tensilica’s Eclipse-based tool chain that is automatically generated for each core. Synopsys has also enhanced its 32- bit ARC extendible embedded processor architecture to target the high memory bandwidth applications such as storage and digital TV and also added support for ARM infrastructure. The ARC HS34 and HS36 processors are the highest performance ARC processor cores to date, handling 1.9 DMIPS/ MHz at speeds up to 2.2 GHz. In a typical 28nm process the cores consume as little as 0.025mW/MHz in an area as small as 0.15mm2. The family uses the ARCv2 instructionset architecture (ISA) coupled with a new Synopsys’ 32-bit ARC HS extendible embedded processor architecture. ten stage pipeline that supports out of order instruction retirement, minimizing idle processor cycles and maximizing instruction throughput. Sophisticated branch prediction and a late stage ALU improve the efficiency of instruction processing and allow a deterministic response for real time performance says Mike Thompson, senior product marketing manager for ARC Processors and Subsystems. SoC peripherals can be directly accessed by the CPU in a single cycle using native ARM AMBA AXI and AHB standard interfaces that are configurable for 32-bit or 64-bit transactions to optimize system throughput. To speed the execution of math functions, the HS cores give designers the option to implement a hardware integer divider, instructions for 64-bit multiply, multiply-accumulate (MAC), vector addition and vector subtraction, and a configurable IEEE 754-compliant floating point unit (single or double precision or both). The ARCv2-based cores provide an 18 percent improvement in code density compared to previous generation ARC cores, reducing memory requirements and support close coupled memory as well as instruction and data cache (HS36 only), with new 64-bit load-double/store-double and unaligned memory access capabilities that accelerate data transfers. Emergency steer assistant avoids collisions By Christoph Hammerschmidt If in road traffic suddenly an obstacle appears in front of the vehicle, drivers have to react within fractions of a second. In many cases, the natural response time of human drivers is too long and a collision renders unavoidable. The European interactiVe project (Accidence avoidance by active intervention for Intelligent Vehicles) now has developed an assistant system aiming at avoiding or at least mitigating such collisions. The German Centre for Aviation and Astronautics (DLR) has tested an Emergency Steer Assistant developed within the scope of the interactiVe project. The system supports the driver in the case of an imminent crash by automatic steering motions. “If in urban traffic suddenly the door of a parking vehicle is opened or if on the highway a slower vehicle suddenly merges in front of you, such an emergency steer assistant can help to avoid a collision”, says Prof. Karsten Lemmer from the DLR Institute of Traffic Systems Technology. In three simulator studies and a real-world trial with the FASCar test vehicle, the researchers investigated the interplay between drivers and the steering assistant. The test drives have been conducted with the FASCar at a speed of 50 kmph (31 mph) on a straight test track. Abruptly, a cable pulled a large net across the road in a way that drivers had no chance to avoid a collision by merely braking. In this test situation the emergency steer assistant was able to perform a dodging manoeuvre at cyberspeed and managed to avoid the collision. In addition, the behaviour of the assistant at higher speeds has been investigated at DLR’s dynamic driving simulator. The test persons had to react to obstacles such as cars that suddenly merged into the driver’s track - a dangerous situation that frequently occurs on motorways. Multiple early warning concepts including acoustic or optical signals as well as assistant system parameters such as the intensity of the steering movement were tested. The trials showed that such an assistant can help reducing the number of accidents with suddenly appearing obstacles. If a collision could not be avoided, its consequences could at least be mitigated. The acceptance of the assistant among the test persons was good. Many drivers did not even realise that the system actively intervened or said afterwards they believed that they acted by themselves with a dodging manoeuvre to the obstacle. Within the interactiVe project, the DLR collaborates with 30 partners such as BMW, Ford and Volkswagen in developing driver assistant systems for critical situations. Along with Volvo Technology Corp, the Centro Ricerche Fiat and Allround Team GmbH, DLR compiled significant findings for design and dimensioning of such collision avoidance systems. Currently the industry partners are working to implement such an assistant system for serial vehicles. A schedule for market introduction however has not yet been submitted. www.electronics-eetimes.com Electronic Engineering Times Europe December 2013 7


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