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MEMORY & DATA STORAGE Bit by Bit, DRAM module testing By Ulrich Brandt Building DRAM memory modules doesn’t seem to be a difficult task. The DRAM technology is well known, components are fully standardized products and the product commodity definition forces the product to be manufactured with low cost materials and assembly lines. If there are no challenges to produce memory modules why are there differences in quality and price? DRAM components are quite complex, although the functionality is somewhat simple. A memory component just has to store information and return it when being read. On the other hand customers require higher and higher density at the same cost. It is almost impossible to find any other electronic component which increases in capacity yet remains the same price as quickly as DRAMs or Flash components. This is accomplished by shrinking the silicon process to smaller feature sizes, each time pushing the predicted manufacturing limits further to the next generation. Where just a couple of years ago a DRAM component with a silicon die area of a few square millimeters offered Mbits of storage, it now offers up to 8 Gbit density. We have lost some of the significance of this. On a state of the art 8GB module there are 64.000.000.000 cells, and not one of them is allowed to fail. The negative side effects of the shrinking roadmap are smaller and smaller electrical charges being stored in the DRAM cells. The memory core operates with lower voltages, increased crosstalk and coupling to neighboring structures. The cell dielectric uses more exotic substances, textures, and aspect ratios to enhance the capacitance, and the highly interwoven cell architecture makes it more susceptible to interference than with older technology. DRAM chip testing and sorting DRAMs are tested multiple times. First they are tested at wafer level where the test looks for weak cells in order to replace them by redundant bits, rows, or columns. In most cases this test is executed not at target speed but with lower frequency settings, and with support by built-in self-test (BIST). The needle prober to contact multiple DRAM dies on the wafer limits the timing frequency. The most complex speed and pattern testing is performed at the packaged level. This testing is often performed at wider temperatures, where the DRAM technology is at the weaker corners. During this testing the speed grade of the DRAM chip is determined, called speed sorting. The component is also tested against known failure modes and with internal test modes to make the test as fast and effective as possible. The optimization of the test is one of the major cost improvements and is addressed by big teams at the DRAM manufacturer. Some DRAMs see special additional tests, while others receive a reduced test flow. This defines if a component is suitable for industrial, automotive or consumer use. The same DRAM part number may have seen different testing depth, and the quality of DRAM components on the spot market can differ from lot to lot. But even if you buy top quality DRAMs from the manufacturer, there is still a handicap to produce top quality modules. As mentioned earlier, DRAMs are built with delicate technology. Exposing the DRAM component to the high temperatures of a solder process causes a lot of stress to the cell capacitor and its dielectric. The cell capacitance and retention time of the DRAM typically degrades during the assembly process. The DRAM manufacturer covers that by applying margins to the testing. There is always a fight between increasing test margin, and a resulting higher yield loss, and the price pressure dictating to keep the margins as small as possible. DRAM module testing Our experience from years of module testing has shown that there are always some weak cells which pass the outgoing test at the DRAM manufacturer and degrade during assembly of the module. These cells have a reduced storage capability and they fail when operated at high temperature and with disturbing write and read patterns. The combination of temperature and noise causes weak cells to lose the information and to sporadically fail in an application. Many module manufacturers rely on the extensive component testing by the DRAM supplier and consider a DRAM as good even after being soldered to a module PCB. Their purpose for testing modules is to detect assembly issues, not weak DRAM cells. To check if the assembly was done correctly simple tests on a module tester or in application boards is enough, and often that is all that is done. But this neglects the degradation effects that the assembly caused to the DRAMs. To verify that no damage has been done to the DRAM components you need to perform quite power- Ulrich Brandt is Head of Business Unit DRAM Products at Swissbit AG – www.swissbit.com - He can be reached at Ulrich.Brandt@swissbit.com Fig. 1: Swissbit’s high speed tester. www.electronics-eetimes.com Electronic Engineering Times Europe February 2013 29


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