031-032-033_EETE-VF

EETE FEBRUARY 2013

MEMORY & DATA STORAGE ful tests on module level and not just at room temperature, but at the specified maximum operating temperature corners or beyond, if you test with guard band. For DRAM components the operation conditions are given as min and max case temperature. This is by default 0°C to 85°C, and for industrial operation -40°C to 95°C. The failure modes at low and high temperature are different. At low temp there are mainly internal contacts failing. At high temperature the cell retention time is the critical parameter. There is no common approach that targets both effects with one test condition. The only guarantee to verify the full functionality of the DRAM cell after assembly is to test the module both at high and low temperature. There are two different approaches to module testing: dedicated DRAM testers or application testing. Both have their respective advantages and limitations. A module tester has a pattern generator, parametric unit, and driver interface. The pattern generator can create address and data sequences, but is often limited to linear addressing modes. There is no possibility of creating more random sequences. On the other hand the tester is very flexible to gauge band timing and voltage levels, and is excellent for debugging. Often the tests are very synthetic and do not resemble the real operation behavior in a PC system. This is the strength of motherboard application testing. The tests can be very similar to the real operation conditions. Fails that you see are relevant, because they occur under conditions that can equally be found during user operation. The application test runs at target speed, and with all the noise and imperfections that differentiates a $200 motherboard from a $1,000,000 high speed tester. The shortcomings of application testing A disadvantage of pure application testing is the impossibility to change timing settings or IO voltages. There is a more hidden handicap of application testing that many are not aware of. In application testing you run the test pattern on the same system that incorporates the device under test. First of all you cannot test 100% of the memory area, since the test program and the OS reserve some memory for themselves. But what’s more, the CPU has to generate the DRAM test pattern with code written in assembly language. It is not very difficult to write fast pattern that linearly walk through the memory and write and compare. But as soon as you go for complex sequences like random address pattern, using calculation intensive operation code with a lot of XOR operations, the CPU is most of the time busy Fig. 3: Swissbit memory test. to generate the next address, and not to access the memory. You need to distribute the test to multiple threads and cores to increase the band width to the DRAM module, and to test it with critical conditions. Using simultaneous multi threading (SMT) in a low level OS like DOS for memory testing is a real challenge and you need years of experience to write memory test programs that exercise the memory with critical pattern in a short test time. If you have this expertise then multi threaded application testing with pseudo random pattern is a very effective tool to find weak cells and to guarantee top quality of a memory module. Another hurdle to overcome in application testing is the support for ECC. This error correction can detect and correct single bit errors of memory modules, something that you want to use as an additional security against bit fails and data loss. In a motherboard that supports ECC the memory controller permanently corrects all single bit errors that occur during testing, effectively hiding all fails from the test program. The test will report “pass” although the memory module had bit errors. This can lead to the situation that ECC modules already have undetected fails that consume most of the error correction capability of the system, rending the ECC worthless. You need to implement support for the chipset ECC generator into your memory testing code in order to detect corrected errors and flag the module as fail. Swissbit combines all of the best of these variables in their module testing. Each module is first tested on a dedicated memory tester, varying timings and IO voltages and measuring leakage. And then each module is tested on a main board with a high performance proprietary memory test that causes maximum cell disturbance and long access pauses in order to drain weak cells and isolate DRAM components that may fail in customer applications at critical high temperatures. All ECC modules are fully supported and 100% tested. For modules with industrial temperature grade Swissbit tests each individual module at -40° and higher than 95°C in order to address both low and high temp failure mechanisms. Each module has been verified at the temperature corners to cover insufficient testing by the DRAM manufacturer and the degradation during the assembly process. With this intensive testing Swissbit guarantees the highest quality, which makes a big difference with modules that have just seen a quick test after Fig. 2: Swissbit burn-in. assembly. 30 Electronic Engineering Times Europe February 2013 www.electronics-eetimes.com


EETE FEBRUARY 2013
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