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MEMORY & DATA STORAGE Moving from magnetic random access memory to magnetic logic units By Bruno Mussard Magnetic random access memory (MRAM) is a new nonvolatile memory technology that is growing in acceptance as a mainstream technology for data storage. It integrates a magneto-resistive device with a silicon-based selection matrix. The key attributes of MRAM are its non-volatility, its low voltage operation, an unlimited read and write endurance, fast read and write operation and ease of integration as back-end technology. These characteristics give MRAM the potential to replace many types of memory in various applications. In its most simple implementation an MRAM cell is composed of a magnetic tunnel junction (MTJ) connected to a select transistor. An MTJ is composed of two magnetic layers separated by a thin oxide tunnel barrier. One magnetic layer has a fixed magnetic orientation and is called the reference layer (FR), the other layer called storage layer (SL) has an orientation that can be switched from one direction to the other. The resistance of the memory bit is either low or high depending on the relative magnetic orientations of storage layer to a fixed reference layer, either parallel or anti-parallel. To read one bit, the select transistor is turned on, and a small read current flows through the tunnel junction as shown in figure 1. The value of the junction resistance is then compared to a reference resistance half-way between the high and low resistance values. Fig. 2 : The Writing procedure in a conventional MRAM architecture (a) and in the TAS-MRAM architecture (b). In the TAS –MRAM writing approach (c), the memory cell write is possible only after overcoming the blocking temperature of the antiferromagnet which pins the storage layer (when the 2 layers are magnetically decoupled). (d) General view of a TA-MRAM stack with both the storage and the reference layer pinned with antiferromagnetic layers. Different MRAMs have been proposed that distinguish themselves mainly by the method used to write the storage layer. A problem, common to all these traditional approaches, is their scalability. As the MTJ is reduced in size, its ability to retain a written data state over time is also reduced. Various methods have been used to counteract this effect but they all imply using much higher powers to write the data making the memory unattractive from an application point of view thus limiting their market penetration. The TAS-MRAM concept To break this vicious circle of low power writability versus data retention, a new approach was proposed called Thermally Assisted Switching (TAS-MRAM). This simple approach uses temperature to differentiate between the properties required for data storage and those require for low writing power. In the TAS-MRAM scheme invented at the CEA/Spintec Laboratory, the magnetic storage layer is modified by adding an antiferromagnetic layer that essentially “blocks” the storage layer’s orientation during read operations. The write process shown in figure 2 then consists of locally heating the junction to a temperature high enough to disable this “blocking” property thus allowing the storage layer to be re-oriented in a low magnetic field. This scheme thus enables a fully scalable bit cell, low power writing and excellent data retention. From MRAM to Magnetic Logic Unit (MLU) The exceptional stability of the stored information obtained using the TAS-MRAM concept has enabled Crocus Technology to develop a new concept called Magnetic Logic Unit (MLU). At the heart of the MLU is a self-referenced (SR) magnetic cell that Fig. 1 : (a) Conventional architecture used in the first MRAM generation containing MTJ cells at the intersection of orthogonal writing lines and on top of a selection transistor. (b) Schematic view of a minor hysteresis loop showing the reversal of the storage layer and two corresponding resistance levels : high “1” and low “0”. Reading (c) and writing schemes (d) used in the conventional MRAM architecture. At read, the selection transistor is ON and a small electric current flows through the MTJ stack, allowing its resistance measurement. At write, the selection transistor is OFF and the combination of 2 orthogonal magnetic fields ensures the selectivity. Bruno Mussard is Security BU Technical Leader at Crocus Technology – www.crocus-technology.com – He can be reached at bmussard@crocus-technology.com 34 Electronic Engineering Times Europe February 2013 www.electronics-eetimes.com


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