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Fig. 3: TAS-MRAM with fixed reference (FR) vs SR-TAS with sense reference (SR). is achieved by simply replacing the fixed reference layer (FR) with a magnetically free layer renamed as the sense layer – see figure 3. As before the resistance of the SR bit cell depends on whether magnetic orientations of the sense and storage layers are parallel or anti-parallel. However, since the sense layer orientation can be controlled using the field line, it becomes a true 3-terminal logic element where the output value is a comparison between the stored data orientation and that of the sense layer defined by the input to the field line. This element acts as an XOR (exclusive OR) logic device. This now allows magnetic elements to be arranged in chains giving NAND type architectures (Lcell) in addition to the traditional NOR memory architectures. In memory applications a differential read is used where the sense layer is switched during read. Only the sign of resistance change defines the stored data state and an external reference resistance level is no longer required. The MLU enables not only rugged and fully scalable memory solutions but also enables new secure functions such as Match-in-Place that are simply not possible with traditional “memory only” architectures. Match in place Crocus Technology has developed an innovative function called Match-in-Place to authenticate users without exposing any confidential data to a security attacker. Fig. 4: Match in Place. Each cell of the Match-in-Place architecture is a non-volatile memory cell combined with the virtual XOR gate of the MLU. Multiple cells are connected in series to create a NAND chain in which confidential data is stored. User data is then applied to the field lines and the resulting chain resistance is either correct or incorrect. If the input data is incorrect (ie does not match with stored data), no information leaves the memory and an information is available as to which bits are incorrect. This is the basis of a linear Match-in-Place engine. If multiple Match-in-Place NAND chains are placed in parallel, they can act in the same time to compare one pattern against many stored patterns. In example of figure 4, a set of 4 MLU cells are connected serially and form a NAND chain that create a linear Match-In- Place engine. The input binary pattern 0011 is compared to the stored binary pattern 1010. Each stored bit is individually compared to the bit of the same rank. The sensitive stored data are never read and exposed to the attacker, the matching cycles can be orders of magnitude more efficient than existing solution in term of speed and power. Match-in-Place engines DESIGNSPARK NEW. FREE. MODELSOURCE OVER 80,000 FREE SCHEMATIC AND PCB SYMBOLS IN MORE THAN 20 FORMATS, INCLUDING PADS, ORCAD, ALTIUM AND CADSTAR. Discover today at www.designspark.com UNIQUE RESOURCES BY www.electronics-eetimes.com Electronic Engineering Times Europe February 2013 35


EETE FEBRUARY 2013
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