037_EETE-VF

EETE FEBRUARY 2013

MEMORY & DATA STORAGE could act as a hardware accelerator, simplify the IC architecture and reduce its overall price. Fields of application for this new architecture are quite wide and include secure microcontrollers, biometric devices and associative memory devices. Use case: secure microcontrollers Crocus has decided to focus on the security business with the development of a high-end secure product family for smart card and embedded microcontrollers. Adding Crocus’ MLU function to the smart card business will give several major advantages including a shorter programming time, easier software development, reliability improvement and a faster personalization time. Compared to existing NOR flash technology, non-volatile memory can be written in a very short time. Programming time can be as a little as 60ns, which speeds up critical write operations around PIN code and keys management. Due to the inherent architecture of the MLU, instruction and data can be written and erased by byte, half-word or word. No page or bank management is necessary. At advanced technology nodes, classic NVMs require complex controllers to handle functions such as wear levelling which are not necessary with MLU technology due to its intrinsically high endurance. One of the important aspects of a smart card product is the need to personalize the programed information, secure operating system or embedded applications to reflect issuer configurations and end-user profiles. Fast programming thus allows significant cost reduction. The MLU-based family of secure microcontrollers from Crocus Technology features a 32-bit secure-core, MLU for Code and Data and contact and contactless interfaces. The very high-end CT32MLU1200 targets EMVco and Common Criteria EAL5+ certification Hybrid Memory Cube gen 2 on track to support a total cube bandwidth of 160GB/s By Julien Happich Last sumer, the Hybrid Memory Cube Consortium (HMCC), led by Micron Technology and Samsung Electronics had released the initial draft of the Hybrid Memory Cube (HMC) interface specification, consisting mainly of an interface protocol and shortreach interconnection across physical layers (PHYs). The specification still needs to be refined for very short-reach PHYs for applications requiring tightly coupled or close proximity memory support for FPGAs, ASICs and ASSPs. While the Gen 1 program was a technology demonstration running at just under 128GB/s bandwidth (over 6x what is expected of DDR4 and 15x the performance of a DDR3 module), Fig. 2: One of the four 16-slice DRAM dies stacked in the Hybrid Memory Cube Gen 1. it was a first step in proving the stacked memory-on-logic concept using a proprietary Through Silicon Via (TSV) process - see figure 1. By stacking 4 DRAM dies vertically, each one configured as a 16-slice device – see figure 2 - with an independent I/O port for each slice, the bottom logic die gets TSV access to all 64 DRAM slices in the stack. With two banks on each slice of the HMC Gen 1 device, this gives users a direct memory access to 128 banks, hence much shorter access latencies. The Gen 2 commercial device for which samples are expected in the second half of this year will use a similar DRAM construction and run SerDes links at up to 15Gbs, for a total cube bandwidth of 160GB/s. “The Gen 2 specifications look rock-solid and the HMC Gen 2 device is rapidly approaching final silicon” commented Dean Klein, Vice President of Memory System Development at Micron Technology. Already looking at Gen 3, Klein mentioned his target, to double the performance of Gen 2 no less. At this stage, without silicon, Micron is characterizing the energy performance (per bit) of the memory devices on simulated parts. Gen 2 has been characterized at about 15.6pJ/bit, that’s half the energy consumption of DDR4 and under a quarter of typical DDR3 energy/bit consumption. “One important aspect of adopting the HMC memory interface is that it will require changes to be made on the processor side, with more SerDes needed” explained Klein. “Companies have already shown their commitments to the technology, and we are a bit in a chicken & egg situation as for the processors that would support such memories. Some of the HMCC members are already developing IP that could readily be integrated into processors to interconnect with multiple high-speed SerDes links” he continued. ”For this reason, FPGA vendors will certainly offer an easier route to integration” Klein concluded. Fig. 1: The Hybrid Memory Cube concept, several DRAM dies stacked vertically on top of a logic interposer. 36 Electronic Engineering Times Europe February 2013 www.electronics-eetimes.com


EETE FEBRUARY 2013
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