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european 3d Tsv summit 2013 Developing and strengthening 3D IC manufacture in Europe By Julien Happich the european 3d tsv summit that took place at Grenoble’s Minatec campus late February gathered 320 attendees from over 20 countries, a testimony of Grenoble’s high tech reputation and France’s competitive edge in the field of 3D IC integration. “There were only local summits so far”, explained Heinz Kundert, President of SEMI Europe, “and this is truly the first time that a conference on 3D Through Silicon Vias (TSV) receives such a global attention, from key European players but also from outside Europe”. “A lot has been spent on R&D and Europe has very good universities, but we also need to maintain a critical mass in IC manufacturing in Europe, otherwise, we could lose our knowhow and critical edge” continued Kundert. There are many issues that need to be addressed for 3D IC manufacture, and now is the chance for Europe to bring IC production back from Asia, according to Kundert. “In highly automated fabs, it may no longer be economical to produce ICs in Asia, especially with all the associated costs of staff travel, and complex machine parts imports/exports”, Kundert highlighted. In fact, there is a reverse relocation trend happening, from Asia to Europe and to the US. As a global semiconductor industry association, SEMI Europe’s role is also to ensure that its members can compete with the Asian and American industry on fair grounds, with the same sort of tax reliefs and energy deals, but also with more education in electronics. In that sense, the European 3D TSV Summit’s recent success helps raise the semiconductor industry’s visibility and get the message across the European Commission. SEMI Europe documents the industry and negotiates with the European Commission on behalf of its members. “The European Commission has now understood that semiconductors represent a key enabling technology for growth in Europe, and this needs to be supported not only with spending in R&D, but also by financing pilot production lines. We are here to raise the issues and to provide a single European strategy for the semiconductor industry, comforting our members that they have a future in Europe” concluded Kundert. Solutions from 2.5D interposers to 3D ICs Although the latest developments around through-silicon vias are aimed at improving direct chip-to-chip connectivity and true 3D IC designs, so-called 2.5D interposers where several chips are connected through an interposer rather than directly using TSVs still have a future. In fact in the next five years, market and technology analyst for advanced packaging at Yole Développement Lionel Cadix expects 2.5D interposers with system partitioning applications to be the biggest drivers for the volume adoption of 3D IC technology. For the global production of TSV chip wafers, the analyst forecasts an impressive compound annual growth rate (CAGR) of 56% between 2012 and 2017, with 2.5D interposer platform wafers shipping at nearly double that rate, growing from less than 100,000 12-inch equivalent wafers today to over 2.5 million in 2017. This is explained by the increasingly complex role that interposers could play in systempartitioning, A typical implementation of a system-partitioning interposer as illustrated by Yole Dévelopment. not only enabling the integration of logic ICs with memory ICs, but possibly allowing designers to mix digital and analog ICs like in a SiP but with better electrical and thermal performances. From a thermal standpoint, 2.5D integration enables similar benefits to those of 3D integration without the thermal drawbacks of overheating, highlighted Cadix. In such system-partitioning, the interposers can act as heat spreaders across the package surface area. 2.5D system-partitioning interposers will often offer a costeffective alternative to all 3D IC design by enabling the use of optimised technologies for each IC (memory, logic, analog, MEMS) with higher yields. This also includes the possibility to cut down large logic chips into several circuits with higher frontend manufacturing yields. The analyst noted that beyond eight cores, processors will lose performance benefits if designed in a 2D configuration. « 2.5D interposers offer a solution to the fundamental bandwidth bottleneck of 2D architectures and will soon be mandatory for increasing the performance of highperformance computers » he concluded, taking the example of Xilinx’ Virtex 7 HT (four slices processed at 28nm on a 25x31mm 100μm thick silicon interposer) or IBM’s next Power 8 multi-core CPU to be based on 2.5D interposers. According to Yole Développement, the 3D TSV market could reach USD 40B in 2017, growing more than 10 times faster than the global semiconductor industry. And 2013 could well be the turning point with the introduction of Micron’s Hybrid Memory Cube. In his presentation, CEA-Leti’s CEO Laurent Malier acknowledged the importance of what he calls smart interposers, an all-encompassing expression for what could include thermal dissipation solutions, and die substrates with integrated passives, photonic interconnects or even active silicon interposers. On CEA-Leti’s 2015 roadmap, the active interposer concept would support SoC partitioning into several dies, with different technology nodes. This enables the faster introduction of new processes, using small dies manufactured at a better yield. The active silicon interposer would integrate not only interconnects but also analog functions, memory control and I/O peripherals. So far, the lab has demonstrated direct face-to-back integration (wideIO memory on a SoC) and face-to-face chip integration (a logic chip on an analog one at 65nm). The ultimate goal would be to achieve modular and stackable logic dies (logic-on-logic), but this would require a 3D network-on-chip (NoC). By 2014, Malier hopes to be able to demonstrate a 3D asynchronous NoC that would support fast serial links and full asynchronous 42 Electronic Engineering Times Europe February 2013 www.electronics-eetimes.com


EETE FEBRUARY 2013
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