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A8E_EE-Times-Eur_2-375x10-875:A8.qxd 4/1/11 1:4 Surface Mount Transformers (and Plug In) and Inductors immediately Pico’s full Catalog onic s . com See picoel e ct r www.Low Profile from .19"ht. logic to avoid clock distribution issues across the stack. The network would include 2D and 3D NoC routers distributed throughout the 2D logic dies. Further on the radar, Malier also mentioned prospective work on a 3D cache memory concept to be stacked on a manycore processor. This would rely on a non-uniform memory architecture capable of splitting cache into multiple banks interconnected with a NoC. The 3D stacking would add flexibility for capacity, high bandwidth and fault tolerance. Such an architecture would require a 10μm TSV pitch and in excess of 10,000 TSVs per chip, compared to the relatively large grain 3D partitioning (50μm TSV pitch) required for logic-on-logic solutions. Audio Transformers Impedance Levels 10 ohms to 250k ohms, Power Levels to 3 Watts, Frequency Response ±3db 20Hz to 250Hz. All units manufactured and tested to MIL-PRF-27. QPL Units available. Power & EMI Inductors Ideal for Noise, Spike and Power Filtering Applications in Power Supplies, DC-DC Converters and Switching Regulators Pulse Transformers 10 Nanoseconds to 100 Microseconds. ET Rating to 150 Volt Microsecond, Manufactured and tested to MIL-PRF-21038. Multiplex Data Bus Pulse Transformers Plug-In units meet the requirements of QPL-MIL-PRF 21038/27. Surface units are electrical equivalents of QPL-MIL-PRF 21038/27. DC-DC Converter Transformers Input voltages of 5V, 12V, 24V And 48V. Standard Output Voltages to 300V (Special voltages can be supplied). Can be used as self saturating or linear switching applications. All units manufactured and tested to MIL-PRF-27. 400Hz/800Hz Power Transformers 0.4 Watts to 150 Watts. Secondary Voltages 5V to 300V. Units manufactured to MIL-PRF-27 Grade 5, Class S (Class V, 1550C available). Delivery-Stock to one week for sample quantities PICO Electronics, Inc. 143 Sparks Ave. Pelham, N.Y. 10803 E Mail: info@picoelectronics.com www.picoelectronics.com Pico Representatives Germany ELBV/Electronische Bauelemente Vertrieb E mail: info@elbv.de Phone: 0049 (0)89 4602852 Fax: 0049 (0)89 46205442 England Ginsbury Electronics Ltd. E-mail: rbennett@ginsbury.co.uk Phone: 0044 1634 298900 Fax: 0044 1634 290904 On CEA-Leti’s 2015 roadmap, the active interposer and the TSV technology that must be scaled down for such solutions. Because each TSV also requires a buffer or keep-away zone (to limit unwanted capacitive couplings and mechanical stress), TSVs need to shrink to achieve surface (silicon real estate) cost reduction. Towards that goal, the lab has demonstrated high-density low diameter TSVs (3μm) across 15μm of silicon. In the future, thermal hot spots could be addressed with integrated graphite heat spreaders, but also with phase change materials for dynamic temperature smoothing, and possibly long distance heat dissipation using a cooling fluid through micro-channels. The challenges for stacking dies into true 3D ICs are not just about process control, TSV density and 3D routing, thermal issues could become the real bottleneck. First, thermal models and design rules must be established. Xilinx’ Senior Director for packaging and advanced technology development, Suresh Ramalingam shared his experience on the Virtex-7 2000T, a 2.5D device that combines a whopping 6.8B transistors across four FPGA sub-dies on a 4-layer metal Si interposer with over 10,000 inter-die connections. Ramalingam insisted on the need for co-design, optimizing dies for extra performance through homogeneous and heterogeneous 3D integration. “With 3D integration using an active die as the carrier (instead of an interposer), you have to decide which chip must go on top”, he said. Ramalingam’s short answer is that the high performance chip should go on top for thermal and TSV process availability (smaller diameter), whilst the bottom die, designed with a more mature technology node should support power TSVs for the top die. Again, it is critical to address the stacked thermal flux with good floor-planning. This calls for multi-physics, multi-die analysis and thermal modelling based on vertical hotspots for which the tools are yet to come, commented Uwe Knöchel, a researcher at the Fraunhofer IIS, Design Thermal flux modelling for a 3D IC stack using Fraunhofer IIS’ internal multi-physics tools. www.electronics-eetimes.com Electronic Engineering Times Europe February 2013 43


EETE FEBRUARY 2013
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