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Automation Division. In fact, “3D IC stacking opens such a big design space that a new class of tools are needed to decide the best design approach. This is particularly difficult because these multi-physics, multi-scale designs exceed the capacity of current simulators”, Knöchel added. You must interface very different tools in order to achieve a thermal-aware floor-planning, for complex designs, Knöchel had to rely on in-house academic solutions. Defining a process flow Eric Beyne, Director of advanced packaging at imec gave us some insights on the manufacturing supply chain needed for a unified 3D IC design flow across foundries and package manufacturers. It could be split into front-end, middle-end and back-end process modules. In the front-end module where the semiconductor device structure and material patterns would be processed, a via-middle approach would consist in fabricating the TSVs after the front-endof line (FEOL) device fabrication, but before the back-end-of-line (BEOL) interconnects. The mid-end process module would include wafer to carrier bonding/debonding, thinning, then backside TSV reveal and passivation, and the addition of a redistribution layer, microbumps and copper pillars. The back-end process would then consist in the actual 3D stacking of the prepared dies and wafers, either die-to-die or die-to-wafer. The consensus in the industry seems to be that TSVs should be scaled down for cost and capacitance reduction. Vertically, this can be achieved by thinning the wafers and by manufacturing high aspect-ratio TSVs. Imec has demonstrated copper vias with an aspect ratio of 10 (5μm diameter, 50μm deep) obtained in a single litho-step. Further on its roadmap, the Belgium university campus sees 30μm deep TSVs with a diameter imec has demonstrated copper vias with an aspect ratio of 10 (5μm diameter, 50μm deep). of only 2μm to be integrated with advanced device nodes. Imec has also demonstrated thin wafer handling (thinning down to 50μm) with backside passivation and copper via exposure. An interesting contribution from Jurgen Wolf, Department Head of HDI WLP/ASSID at Fraunhofer- IZM / ASSID was to showcase the institute’s capabilities for etching TSVs with an aspect-ratio of over 12 (10μm/120μm and 5μm/60μm+) and the development of nanoporous european 3d Tsv summit 2013 gold bumps for chip to substrate bonding. The new Ag/ Au alloy chemistry used for bump deposition can be used in a conventional Au bumping process flow. The nano-sponge is obtained through de-alloying by wet etching the aluminium. This sponge-like gold bumps have an average pore sizes adjustable from 20nm up to 500nm and are fully compressible and able to compensate topography issues on chip and substrate, which can also be an issue for die-to-die and die-to-wafer stacking. Frederic Voiron, Senior R&D Engineer at IPDIA gave a good illustration of what 2.5D passives interposers could bring into the equation. Thanks to his company’s passive integration connecting substrate (PICS-IPD), hundreds of passive components could be integrated into a single silicon interposer, he said, claiming the world record of capacitance density in silicon, with 250nF/mm2 in production (on 100 μm wafers) and 500nF/mm2 tested and demonstrated. The technology could be combined with TSVs to build system-in-package solutions or even passive dies stacking for volume-constrained application. Thorbjörn Ebefors, Chief Technologist, co-founder and VP of R&D at Silex Microsystems had a particular eye on TSVs for MEMS solutions. For MEMS applications, TSVs are used either through the sealing cap or through the bulk substrate and at much lower densities, typically 1 to 10 TSV/mm2. They allow for compact MEMS-ASIC packaging, either wirebond or flip chip. The TSVs can be built directly into the MEMS substrate, eliminating the need for an organic substrate or interposer altogether (all-silicon package). Silex Microsystems offers two types of TSV technologies: the Sil-Via rigid interposer developed in 2003 across the full wafer thickness and a more recently developed Met-Via baseline process released in 2010, for TSVs through the MEMS cap. The ability to create TSVs through full wafer thickness means the interposer can be the package, using existing wafer processing, without exotic thin wafer handling. Again, the silicon substrate can be “functionalized” with passive or active elements. For example the MEMS cap wafer could integrate vertical capacitors, but also inductive coils with a magnetic core for driving the MEMS structures. Nano-porous gold bumps for chip to substrate bonding by Fraunhofer- IZM / ASSID IPDIA’s passive integration connecting substrate (PICS-IPD) with its embedded capacitors: concept and micrograph. 44 Electronic Engineering Times Europe February 2013 www.electronics-eetimes.com


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