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EETE FEBRUARY 2013

A32E_EETimes2.375x10.875_A32.qxd 1/4/13 12:36 PM The latter can be realized as a combination High Voltage to 500 VDC OUT. High Power to 50 Watts. Regulated/Isolated DC-DC Converters QP Series Isolated New Input Voltages available 125-475 VDC (Consult Factory) High Voltage, Isolated Outputs 100-500 VDC Output Voltages from 500VDC High Power: to 50 Watts, Efficiency to 90% Miniaturized Size package: 2.5" x 1.55" x 0.50" Safe: Short Circuit, Over/Under Voltage, and Over Temp. Protected Options Available: Expanded Operating Temperature, -550C to +850C Environmental Screening, Selected from MIL Std.883 Ruggedized for Operation in Harsh Environments External Bias Control: For Charge Pump Applications Custom Modules: Available to optimize your designs, Special Input or Output Voltages Available Rely on Pico for Thousands of ULTRA Miniature, High Reliability DC-DC Converters, AC-DC Power Supplies, Inductors and Transformers www.picoelectronics.com E-Mail: info@picoelectronics.com PICO Electronics,Inc. 143 Sparks Ave, Pelham, NY 10803-1837, USA Call 800-431-1064 Pico Representatives Germany ELBV/Electra Bauemente Vertrieb E mail: info@elbv.de Phone: 49 089 460205442 Fax: 49 089 460205442 England Ginsbury Electronics Ltd E-mail: rbennett@ginsbury.co.uk Phone: 44 163 429800 Fax: 44 163 4290904 of Met-Via TSVs and copper-traces on the wafer’s surfaces with a layer of FeNiCo alloy trapped into the windings. 3D stack testing Working with known-good-dies won’t be enough to secure high 3D IC yields, and new testing strategies need to be developed. Design-for-test is the way to go, was the main message from Brandon Wang, Director 3D IC and Advanced Technology Silex’MEMS cap wafer could integrate vertical capacitors, but also inductive coils with a magnetic core for driving the MEMS. Product Management at Cadence Design System. First you need the tools for design partitioning, at different technology node for each die, then you must look at the die orientation and stacking orders, and last you must analyse performance (delay, latency), power distribution (thermal issues) and mechanical stress. This calls for a co-design between the package, the IC stack and the interposer for optimized TSV and bump locations, cross die bump optimization and best power plans. This is when you must design the interconnects and die-internal circuitry to ensure test access at the bottom die, in a way that allows test stimuli and response propagation up and down through the final 3D stack. This systematic approach requires new layout rules. In collaboration with imec, the EDA company has implemented and validated an automated 3D Design-for-Test (DFT) solution to test logic-memory interconnects in DRAM-on-logic stacks. Based on Cadence Encounter Test technology, the solution was verified on an industrial test chip containing a logic die and a JEDEC-compliant Wide-I/O Mobile DRAM (on an interposer). The solution supports post-bond testing of the interconnects between the logic die and the DRAM stacked on top of it. It also includes the generation of DRAM test control signals in the logic die and the inclusion of the DRAM boundary scan registers in the serial and parallel test access mechanisms (TAM s) of the 3D test architecture. The inserted 3D DFT wrapper IP had a negligible impact on die area, at about 0.3% of total circuit silicon footprint. Wang also disclosed a thermal analysis flow and an IR drop analysis flow where all the micro-bumps and TSVs are modelled as RC or RLC networks while all the chips are analysed at the same time for accurate results. So what about accessing these tiny test pads at the bottom of the stack? Senior Director for Business Development at Advantest, Gary Fleeman hinted at MEMS-based micro-probe tips that would not break the thin wafers nor dig marks on the copper traces. Advantest is evaluating the InfinityQuad probe technology developed by Cascade Microtech, with monolithically fabricated tips at a 40 μm pitch, with a positional accuracy to within 1 μm and excellent planarity (a prerequisite for good contact yield). Another MEMS-based approach under development from sister company TouchDown Technologies relies on a swinging probe tip that would yield lower tip forces (under 1 gram-force) for a lesser pad damage. In principle, such approaches would be scalable to finer pitches. New MEMS-based micro-probe tips from TouchDown Technologies could rely on a swinging probe tip to yield lower tip forces for a lesser pad damage. www.electronics-eetimes.com Electronic Engineering Times Europe February 2013 45


EETE FEBRUARY 2013
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