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7-in-Oneders of Picoscope 1. Oscilloscope 2. Spectrum analyzer 3. Function generator 8th Come and see the 8th wonder on stand 4-436 at embedded world 4. AWG 5. Logic analyzer 6. Serial protocol analyzer 7. Automatic waveform test www.picotech.com/PS280 tion specificity of MEMS collectively, at a wafer-level process instead of packaging individual dies”, Zinck explained, mentioning ASE’s new 3D WLP tool box for standardized operations in complex MEMS architecture. “What’s more, the standardization allows for volume production, enabling second sourcing and cost efficiency through technology sharing” concluded Zinck. Since 2013, the company is in volume production for full wafer-level packaged MEMSs using TSVs for chip-to-wafer assembly. The tool box presented by ASE includes wafer-level capping, wafer-to-wafer or chip-towafer assembly, wafer moulding, TSVs, and wafer-level redistribution and balling. On its 2015 roadmap, the OSAT plans thin film MEMS capping, wafer-to-wafer metal bonding and sealing, WLCSP of any MEMS connected on top of any ASIC using TSVs, or on top of active interposers embedding on or several ASICs. Who should manufacture TSVs? In non-MEMS ICs, TSVs must shrink too, because going to the next generation node does not necessarily make sense if your TSV keep-out zone takes too much premium silicon. The processes require equipment sets typically seen in wafer fabs, hence TSV integration could be done by the foundries, but also to some extent by OSAT service providers (Outsourced Semiconductor Assembly and Test). Some printed circuit board (PCB) makers are also looking at embedded dies into PCB substrates, in the form of active interposers for 2.5D integration. Putting aside the current economic climate which could limit TSV ramp up in the near term, Gartner’s Mark Stromberg expects the TSV market to faces capital cost issues that will limit the number of companies able to implement this technology. This is due mainly to the additional capital and material costs, together with more process steps. “As we move to the 10nm node, TSV technology will be require for system design”, Stromberg said, noting that the cap-ex requirements will reduce competition with only the top Integrated Device Manufacturers (IDMs), foundries and top tier Semiconductor Assembly and Test Services (SATS) able to compete. Dr. Miekei Ieong, Vice President of TSMC EMEA, presented his company’s CoWoS (Chip-on-Wafer-on-Substrate) services relying on through silicon via technology to integrate multiple chips into one single package using a submicron scale silicon interposer. The company offers homogeneous CoWoS in production but says it has already demonstrated heterogeneous CoWoS. A 512-bit Wide I/O DRAM test chip was operated at 200MHz and even overdriven up to 285MHz with full operations. “Our 1024-bit TSMC CoWoS DRAM was driven to 1GHz, supporting a bandwidth up to 128GB/s”, said Ieong, with plans to tape-out daisy-chained 6 top dices high bandwidth memory by the last quarter of this year. For the purpose of larger Co- WoS, TSMC has also demonstrated silicon interposers up to 26x48mm on a substrate size of 60x60mm. The company says it is ready for stacking memory chips on 28nm logic, and it has characterized TSV design rules for customer’s test vehicle design and functional verification. Global Foundries’ Michael Thiele, Responsible for Packaging R&D, exposed his company’s readiness with TSV-capable lines installed in Malta, New York, with TSV integration characterized for 20nm devices and 14nm under way. The company has a 300mm TSV line installed in Singapore for Si interposer fabrication and is characterizing TSV integration into 28nm devices in Dresden, Germany. www.electronics-eetimes.com Electronic Engineering Times Europe February 2014 21


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