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EETE FEB 2014

“Before considering a 2.5D product tapeout, customers expect the foundry to come up with system level qualification data from a representative test vehicle”, stated Thiele who then unveiled Global Foundries’ dual approach, using external test vehicles with shared R&D but also creating its own internal test vehicle. Hence, the company develops interposers and micro-pillar interconnects both at OSAT partners and in-house. But Thiele stressed that yield loss, late in the supply chain, could stop the adoption of the technology, especially if there is not a clear yield ownership in the supply chain. Cost reduction at key process steps such as TSV drill and fill, temporary wafer bonding and de-bonding, TSV reveal, is another must for 3D ICs to make it to the mass market. Cutting on materials and process costs Director for Industry Development at the A-star Institute of Microelectronics (IME), Surya Bhattacharya sees back-end of line (BEOL) and thin wafer handling (including temporary wafer bonding and de-bonding - TBDB) as a real cost-issue for 3D IC components. These added processes alone amount to around 50% of the total final component cost, he estimates. Bhattacharya’s drastic cost-cutting approach is to rely on low-cost multi-level copper redistribution layers (Cu RDL) in thick photo-dielectrics (polymers), requiring fewer processing IME carrier-less process flow using wafer-level over moulding. steps, no CMP steps and no dielectric etch. The lab has developed photoresist materials and has demonstrated Cu RDL fabrication for different line widths and spacing, at 5/5μm and 3/3μm, with three levels of metal. The copper redistribution layer with a line width of 3μm and a polymer pitch of 6μm was demonstrated to support 20Gbit/s signals across a 10mm interconnect, versus 7.5Gbit/s for the costlier 1μm wide copper line in a damascene structure, at a 4μm pitch. The lab is also experimenting with 2μm thin copper lines in polymer, and targets 0.5μm line width by 2016 to stay competitive with very fine TSVs. On top of this approach, Bhattacharya exposed a carrier-less technique to avoid or reduce the TBDB steps, whereby after chip-to-wafer bonding and underfilling, the full wafer is over moulded and flipped for backside via reveal, directly maintained by the epoxy mould compound. Altogether, removing the back end of line (BEOL) Cu RDL deposition processes and the TBDB steps, Bhattacharya roughly estimates that wafer-level processing costs could be slashed by 40% to 50%. “Moving from a copper and damascene structure to a copper redistribution layer into an organic layer can cut 15 to 20% of your processing costs” concurred Sesh Ramaswami, Managing Director for Packaging Technologies and Advanced Product Technology Development for the Silicon Systems Group at Applied Materials. One way to reduce the lengthy and costly CMP process is to fine tune the 3d tsv summit Electroless Cu conformal barrier-seed deposition technique could slash 50% of the process costs associated to TSVs, compared to using I-PVD. growth of the via and the subsequent via reveal step so as to stop the etch right when the vias are revealed, with only little material to remove during the Chemical Mechanical Planarization to open the vias and trim them down to the wafer surface. Director of Process Technology at Tel Nexx, Steve Golovato exposed a cost of ownership analysis for high aspect ratio TSVs built up using conformal barrier-seed deposition. Using this particular TSV filling, Golovato says the industry could contain CMP costs compared to using Ionized PVD barrier-seed deposition which can create a material overburden atop the via (and requires more CMP to be removed). More interestingly, Golovato expects his company’s electroless Cu conformal barrier-seed deposition technique to be up to 50% lower cost than I-PVD for TSVs with an aspect ratio of 20, at wafer-level. Precise via reveal Vice President of Marketing at SPTS, David Butler aims to minimize the CMP step by optimizing the via reveal step. SPTS has developed Deep Reactive-Ion Etching (DRIE) equipment capable of etching at rates up to 4.7μm/mn (with a uniformity of ±3.0%). That is twice as fast as competitors, according to Butler, and up to four times faster than wet-etch approaches. Another important advance is SPTS’s ReVia in-situ end-point detection. Based on IR interferometry, this automated optical analysis feature looks at groups of vias across the surface being etched and is able stop the via-reveal process when via tips emerge, only 1μm above the surface. This avoids costly rework operations, typically more etch if not all the vias are revealed, or yield issues if the wafer is etched beyond usability. The company also implements dual source tuning for etching, which allows its equipment to tightly control etching across the wafer, radially. This can be used to compensate for wafer thickness variations after the wafer thinning step. Last, the company introduced its Rapier XE, its next generation equipment capable of etch rates up to 9μm/mn entirely tuneable radially and promising four fold productivity gains. SPTS’s via-reveal process implementing ReVia in-situ end-point detection. 22 Electronic Engineering Times Europe February 2014 www.electronics-eetimes.com


EETE FEB 2014
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