Page 48

EETE FEB 2014

AUDI O & VIDEO PROCESING 12Mbits/s in the down-link. The demonstration system consists of a master circuit and a peripheral circuit - see figures 1 and 2. (In an actual end product design, the master circuit would be embedded in the mobile device and the peripheral circuit in the control part of the headset.). To provide for a single power supply, the battery is connected to the master board, where various voltage levels are generated. The peripheral board is supplied via the mic-wire of the 3.5mm connector, which carries the modulated microphone signals as well. A main clock is generated on the master board, and the peripheral board is synchronised with it. The partitioning of the functional blocks can be seen in figure 3. Both the master circuit and the peripheral circuit consist of two boards sandwiched together. Master board A provides the power supply, clock generation via a PL, digital circuitry for data preparation, lock-out detection and – the core block – the combined data modulator/demodulator. So this board contains the main functionality of the data transfer system. Master board B contains the application circuitry: a DAC converting digital microphone signals to audio signals, audio amplifiers, the AS3430 ANC chip, filters, a microcontroller and an LCD. Peripheral board A contains the supply LDO, the sync- and data-extractor, data modulator, control buttons, and the main microphone (for sensing the user’s voice). Peripheral board B contains the PL and the control logic for data manipulation. Then a headphone set is connected to the peripheral board: the headphone features two additional microphones to pick up the ambient noise that should be suppressed. The main clock frequency generated at the master board is 2MHz. This is used to modulate a saw-tooth voltage around the 3V mic-wire supply to the peripheral board. At the peripheral board, an internal supply Fig. 4: Timing diagram of voltage modulation scheme. of 2.2V is extracted; the falling edges of the saw-tooth voltage are used to reconstruct the 2MHz clock. (In order to ensure the digital components operate properly at this low 2.2V supply, TTL-gates on the peripheral boards are taken from the LV/LVC series.) The saw-tooth voltage frequency controls a PL that generates the master clock of the peripheral circuit. Since the same PL circuit is implemented in the master Fig. 5: Timing diagram of current modulation scheme. board, both devices operate synchronously - this avoids problems with sampling of the transmitted data. When data is to be transmitted from the master board to the peripheral board, the size of the saw-tooth steps is ample for the coding required - see figure 4. Two levels are sufficient for ‘High’ and ‘Low’ signals; a third can be used for synchronisation purposes. An upstream data rate of 2Mbits/s is possible with the selected clock frequencies. While upstream transmission is achieved through voltage modulation, downstream data transfer from the peripheral board to the master board is realised with current modulation. Although using the same mic-wire, the up- and down-link data streams do not interfere with each other if the circuit is carefully designed. First, the circuit that injects the saw-tooth ripple into the DC voltage at the master board must have low impedance, to ensure that the current modulation does not disturb the voltage signal. Second, the current demodulator on the master board must be insensitive to the voltage variations on the mic-wire. In addition, the current consumption of the peripheral board has to be more or Fig. 3: Block diagram showing partition of functions between the master circuit (the mobile phone in an end product design) and peripheral device (headset controller in an end product design). 32 Electronic Engineering Times Europe February 2014 www.electronics-eetimes.com


EETE FEB 2014
To see the actual publication please follow the link above