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EETE FEB 2014

PROGRAMING TOOLs & DESIGN KITS Hardware designers take on the software challenges of verification By Nick Flaherty testing the software in a complex System on Chip (SoC) design is an increasingly important challenge, and two UK tool developers have come from chip design backgrounds to tackle that problem. Development kits and integrated development environments can take the project so far, but the two companies are taking a different approach to verifying complex code on such designs. Engineers at Cadence Design Systems working on the Verisity tool saw an opportunity to take the techniques we use for testing system on chip devices and apply them to the challenge of testing software. With millions of lines of code, many software projects are approaching the complexity of SoC devices from a few years back. So engineers took the coverage driven verification (CDV) test technology that is standard in hardware as the basis for Coveritas to apply to system code. Argon Designs in Cambridge similarly has developed a compiler for executable specifications so that the standard can be fully tested with directed random streams of data. Their focus is on the HEVC video compression standard (also called H.265) that is emerging to reduce the bitrate of HD and UltraHD video. The founders of Argon were previously with chip designer Alphamosaic and come to IP verification from a chip angle rather than a software one. The Argon tools take the specification and compiles the pseudocode to generates the minimum streams of test data that can validate the decoder IP against the original specification. “What’s good about the formal specification approach is that by making the streams check the specification against the code you can choose either the specification or the code as the golden reference,” said Peter de Rivaz at Argon. “Once we have the formal specification we can apply code transformations for example to measure line by line branch coverage and cross coverage, checking macro blocks.” “We have a mode that can trace through the specification and understand the maximum and minimum range for any symbol at any point. This is particularly important in HEVC and motion prediction as you have 16 cases that all fit into 16bits, except one. As a result the streams are compliant and measurable.” The ability to produce an executable model of the spec to generate the test streams means the team found over 60 bugs where the reference silicon implementation differs from the specifications. This matters to the system code developers – do they change their code to pass the reference decoder and risk that changing in the future, or stick with the standard. Fig. 1: sample output from an Argon Stream. 38 Electronic Engineering Times Europe February 2014 www.electronics-eetimes.com


EETE FEB 2014
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