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neural networks in the artificial neural network. “Deep learning isn’t a science project” for Google, said Bier. “It gives Google clear, commercial advantage for its business.” The alliance with Movidius won’t preclude Google from working with other embedded vision SoC vendors. Surprisingly, though, very few embedded vision SoCs are on the market today, said Bier, although there are silicon IPs now available from companies like Ceva, Cadence and Synopsys. Chip vendors are using everything from CPU and GPU to FPGA and DSP to enable CNN on vision SoCs. But when it comes to chips optimized for embedded devices like wearables, “You need a chip that costs less and runs at very low power,” Bier said. Qualcomm is offering embedded vision on its “Zeroth platform,” a cognitive-capable platform. Some system vendors are using Xilinx Zynq FPGA for it. Cognivue, now a part of NXP Semiconductors, claims a chip designed for parallel processing of sophisticated Deep Learning (CNN) classifiers. But NXP’s focus is solely set on automotive, a growing market dominated by Mobileye. A swerve towards CNs Movidius CEO stressed, “It’s one thing to talk about theories, but it’s another to deploy CNN on a commercially available chip on milliwatts of power.” El-Ouazzane acknowledged that when the company first developed its computer vision chip, “We weren’t necessarily thinking about CNN.” But in the last few years, “we’ve seen the industry’s accelerated interest in the use of CNN in the cloud.” It turns out that Movidius’ chip, serendipitously, is well designed for artificial intelligence neural networks. Google picked Movidius because the startup’s latest chip, MA2450, is the only chip commercially available that can do machine learning on the device. MA2450 is a member of Movidius’ Myriad 2 family of vision processing unit SoCs. Myriad 2 provides “exceptionally high sustainable on-chip data and instruction bandwidth to support the twelve processors, 2 RISC processors and high-performance video hardware accelerators,” according to the company. A close SHAVE In particular, it contains a proprietary processor called SHAVE (Streaming Hybrid Architecture Vector Engine). SHAVE contains wide and deep register-files coupled with a Variable-Length Long Instruction-Word (VLLIW) controlling multiple functional units including extensive SIMD capability for high parallelism and throughput at both functional unit and processor levels. The SHAVE processor is “a hybrid stream processor architecture combining the best features of GPUs, DSPs and RISC with both 8/16/32 bit integer and 16/32 bit floating point arithmetic as well as unique features such as hardware support for sparse data structures,” explained Movidius. MA2450 is an improvement on the company’s MA2100, according to El-Ouazzane. The MA2450 uses TSMC’s 28nm HPC process, while MA2100 uses TSMC 28nm HPM. Computer vision power in MA2450 is one-fifth of that of MA2100 and the power of MA2450’s SHAVE processors has been reduced by 35 percent. MA2450’s memory increased to 4GDRAMigabit Fig. 2: The segments of the image are fed through nodes of the convolutional network. They start to differentiate not at the pixel level, but at the feature level (ie. Paws, whisker, etc). CNN is far better at classification than older approaches where the programmer must explicitly code a set of rules. (Source: Movidius) DRAM from MA2100’s 1Gbit. The 2 32-bit RISC processors inside MA2450 run at 600MHz, compared to 500Mhz in the older SoC. Meanwhile, the industry’s interest in deep-learning-based computer vision is rapidly growing. Bier said the Embedded Vision Alliance is offering a tutorial on CNN and a hands-on introduction to the popular open source Caffe framework on February 22nd with primary Caffe developers from the Berkeley Vision and Learning Center at U.C. Berkeley. Fig. 3: Myriad 2’s special micro-architecture (Source: Movidius). www.electronics-eetimes.com Electronic Engineering Times Europe February 2016 19


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