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EETE JANUARY 2013

RFID TECHNOLOGIES Identifying UHF RFID tag design weaknesses By Myriam Massei UHF RFID tags put on the market the RF carrier energy down converted should all be compliant with the standard into a DC voltage (Vdd). to implement EPC gen 2. Nevertheless the perfor- this function the designer commonly mances can be very different from one uses a rectifier together with a regula- tag to another. as an example, NRFLab tor block. the consequence is that the did a benchmark of several tags which power supply will vary over temperature, resulted in noticeable tag performance RF frequency range and input power differences. The lower performances of (more than 30%). Overall, this means a tag can either restrict its use at shorter that the tag is not designed to guarantee distances from a reader or require the Fig. 1: Basic RFID tag architecture. a robust performance. use of a high quality detection and cor- For example the clock reference that rection tag reader. will define the precision of the backscat- after reviewing various tags and ter link frequency (BLF) and the total reader architectures, we’ll use the tags’ length of a binary (tari) is composed performance results obtained through mostly by 3 or 5 inverters looped back. testing and offer some solutions to im- this architecture is very sensitive to prove the poor-performing tags. the power supply, the temperature and process. the tag’s response signal will RFID tag design weaknesses depend on a non-robust load variation, a typical RFID tag includes an antenna, with a non-predictable time response a front end radio and a digital cell as and at least with a very low level signal, shown on the tag’s architecture of figure Fig. 2: RFID tag front-end architecture. at least compared to the input signal 1. The front-end radio – see figure 2 - is generated by the reader. to compensate composed of a power rectifier followed those imperfections at tag level, the by a regulator, a very simplified clock design constraints will be on the reader’s reference, a demodulator block receiver architecture. and a load modulation transmitter as detailed on figure 3. First, the reader architecture must be able to detect small signal response the front-end radio architecture of an in a non-predictable delay and non- RFID tag reader is much more complex constant RF response type: module and includes an antenna, a regulated and/or phase (or I/Q signal). that’s why power supply, a synthesiser calibrated to Fig. 3: RFID tag transmitter architecture a homodyne receiver structure is used. generate the RF carrier using an exter- (charge modulation). And the first stage receiver is composed nal clock reference, a heterodyne RF of a Low Noise Amplifier to amplified receiver and a polar modulation RF transmitter – see figure 4. small RF signal without amplifying the noise. secondly, the the cost and time development of a reader is thus much more reader provides the RF carrier signal during all the communica- important than for a tag. tion, whether it’s reader to tag or tag to reader. It needs a robust synthesizer architecture using an external quartz to generate Why are the two architectures so different the RF carrier. thirdly, during the transmission (reader/ tag) the and how does it impact performance? reader generates and modulates the RF carrier. During signal Usually, the RFID tag’s front-end radio design is simplified as reception (tag to reader), the reader still generates the RF carrier much as possible to reduce its development cost and chip and measures the signal response modulated by the tag. as the size. as an example the transmit signal generated by the load tag’s receiver is nonlinear, the modulated signal transmitted by modulation transmitter is not a pure real load variation or a pure the reader to the tag can be nonlinear, but the power level must imaginary load variation. the load varies over frequency. as a be very high (more than 16dBm). the transmitter architecture result the reader’s architecture must be able to detect and de- often chosen for its best efficiency and low linearity is a polar modulate a real and/or imaginary load variation. secondly, the modulation structure. demodulation receiver is nonlinear. It only generates a 1-bit signal (1/0) for the digital block. Bench mark analysis additionally, the UHF RFID tag is passive which means that the Based on the benchmark results shown on graph 1 and 2 for power supply of the tag needs to be generated internally, using nine RFID tags put under test, we have chosen two tags with different performances, namely the tags 9 and 7. Myriam Massei is CEO and designer at NRFLab - www.nrflab.com thanks to additional tests and performances analysis (ob- – she can be reached at massei.myriam@nrflab.com tained through the NRFLaB test platform for UHF RFID tags) 40 Electronic Engineering Times Europe January 2013 www.electronics-eetimes.com


EETE JANUARY 2013
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