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EETE JAN 2014

PASSIVE COMPONENTS Silicon capacitors: a new solution for decoupling applications By Laëtitia Omnès As consumers are eager to get the most cutting-edge products, manufacturers have to adapt their technologies and continue to drive innovations to offer the most advanced electronic equipment. Two key features must often be considered for electronic devices: size and performance. In order to anticipate the demand for more miniaturization and signal integrity over a wide range of frequencies in the decoupling applications, IPDiA adds to its silicon passive component library some ultra low ESR/ESL structures, in low profile form factor. These new silicon capacitors enable to drastically decrease the overall impedance and offer the best solution for decoupling performances up to 10 GHz frequency range. In the case of embedded applications and System in Package modules, not only must the size of the device be optimized in x and y axes, the thickness is also highly important. IPDiA provides a full range of silicon capacitors, including some with ultra-low profile - down to 30 μm - developed and offered for decoupling applications with space constraints. In terms of performance for decoupling applications, the main feature that needs to be improved is the signal integrity of the integrated circuit. On top of the low profile feature, these applications Fig. 2: Standard PICS capacitor design compared with Mosaïc PICS capacitor design. The ESR is driven by the capacitor shape/outer extend in the standard design when it depends on the localized element in the Mosaïc. ESRGlobal becomes a variation of 1/N in the second case, N being the number of elementary cells parallelized. are very demanding in signal integrity and decoupling capacitors are considered to be one of the best solutions in terms of efficiency and cost to reduce the voltage fluctuation. However, decoupling capacitors are not perfect and their performance depends not only on the capacitance but also on the Equivalent Series Resistance (ESR) and on the Equivalent Series Inductance (ESL). The total ESR is the sum of the resistance of the dielectric material (frequency dependent) and the resistance of the conductive parts (constant value). For a long time, ESR was the main parameter to be considered. But as the race for higher-speed applications gathers pace, capacitors with low impedance at highfrequencies are needed. This trend leads manufacturers and designers to take into account the ESL parameter. This further complicates the Fig. 1: 100 μm die embedded in a PCB. work of designers, who need to consider the constraints imposed by these parameters. The IPDiA R&D team has addressed this issue with its high density capacitors. Ultra low profile silicon capacitors The manufacture of IPDiA passive components is based on the PICS (Passive Integration Connecting Substrate) developed in IPDiA’s own R&D center. This technology takes advantage of the thickness of silicon to integrate hundreds of passive components such as high-Q inductors, resistors, MIM capacitors and trench MOS capacitors in one single die. This technology has already proved its efficiency in terms of area saving. The 3D trench depth of the silicon capacitor drives the results obtained in terms of thickness and capacitor density. Table 1 shows the die thickness obtained and the corresponding capacitor density, figure 1 shows a 100 μm die embedded in a PCB. On top of the low profile specificity, these 3D silicon capacitors, already in mass production, offer a capacitance density up to 250 nF/ mm² with a breakdown voltage (VBD) of 11V minimum. Their “Intrinsic lifetime” t0.1% is over 10 years at 3.6V, 100°C (60% C.I.) even for corner batches. The devices have low leakage (typically < 5 nA/μF and down to < 0.2 nA/μF at 3.2V/25°C), and a high capacitance stability with respect to temperature (70 ppm/°C over the -55°C/+200°C range) or voltage (<0.1%/V). ESR/ESL contribution To cope with the increased demand for more sensitive devices and faster transition in the IC, power integrity must be guaranteed and therefore impedance minimized while maintaining the availability of a wide range of capacitance values. The output ripple voltage is directly related to ESR values. As input/output voltages of modern DC/DC converters are getting lower and lower, this input/output ripple due to ESR is an increasingly important parameter that has become challenging to solve with standard MLCCs. In the past decades, all capacitor parameters were measured at a standard of 1MHz, as DCDC converters were operating at 10MHz. But in today’s high frequency world where the trend in DC/DC converters is to operate in ranges of tens of MHz, this is far from sufficient. Ideal values for a good high frequency capacitor for a given capacitance could run in the order of about Laëtitia Omnès is responsible for Marketing and Communications at IPDiA – www.ipdia.com – She can be reached at laetitia.omnes@ipdia.com 32 Electronic Engineering Times Europe January 2014 www.electronics-eetimes.com


EETE JAN 2014
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