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EETE JAN 2015

circuit integration Monolithic 3D integration cheaper than moving to next node By Julien Happich During a 3D-VLSI workshop preceding IEDM 2014, in San Francisco, CEA-Leti presented its latest results on multi-layer transistors stacking for true 3D monolithic integration, that is without relying on tall through silicon vias (TSVs) and coarse redistribution layers typically used for wafer-on-wafer die stacking. Only recently dubbed CoolCube for its future commercialization, the technology can be essentially described as sequential 3D ICs manufacture, enabling circuit partitioning in 3D at all granularity levels, including at transistor or gate scale through a standard lithographic process. The key difference with the “traditional” use of TSVs, where two or more processed dies are assembled one on top of another, is the transfer and molecular bonding of a thin Si wafer film, peeled off from a wafer blank after planarization. Because the transferred film is so thin and optically transparent, well under a micron (compared to around 50 microns thin for thinned wafers), the new layer of transistors that are processed on top can be aligned to the bottom transistors with lithographic precision. Hence the stacked layers can be connected at the transistor scale rather than just through the dies’ metal pads. This approach was only possible through the use of a lowtemperature budget MOS transistor technology on top, the “COOL” layer processed under 600ºC so as not to alter the first bottom MOS transistor layer. This low-temperature fabrication allows vertical integration of a transistor without degrading the performance of the transistors beneath or the metal interconnects between the layers of the transistors. In a paper titled “3D sequential integration opportunities and technology optimization”, Leti’s Advanced CMOS Laboratory Manager Maud Vinet describes the necessary 3D contact process between the two layers as being marginally higher than a standard tungsten contact plug in an oxide, with an additional height of the 3D contact in the range of 50nm. The cool process relies on Solid Phase Epitaxial Regrowth (SPER) for dopant activation by recrystallization at temperatures between 450°C and 600°C (effective down to 500ºC without any impact on the bottom layer). This is about half the typical thermal budget for manufacturing transistors (around 1000ºC). “This is really different from using TSVs, which are several orders of magnitude bigger than these contact plugs”, explained Vinet during an interview with EETimes Europe. “We are using a classic front end process, these 3D vias are in the range of 100nm with a very small diameter and do not require a keep-out zone (as TSVs do)”, she added. Overall , this approach could support an via density up to 100millions/mm2 between layers while allowing for different materials and processes to be stacked one upon the other. Using 14nm node design rules FDSOI transistors, the research team at CEA-Leti worked on a 3D monolithic FPGA stacked on two levels, with memory cells placed in the bottom layer and the logic cells in the top one. Compared to a 14nm planar FDSOI integration and thanks to the dense vertical interconnects, the 3D stacked design shrinked 55% in area and nearly halved the Energy Delay product. Another step in the more-than- Moore race, this 3D monolithic integration enables a 30 percent increase in speed compared to the same technology generation in classic 2D. “In effect, we had more than one node gain by stacking N-1 over N-1 as compared to node N in a planar process”, concluded Vinet. 18 Electronic Engineering Times Europe January 2015 www.electronics-eetimes.com


EETE JAN 2015
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