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MEMORY & DATA STORAGE and medium storage densities.” In comparison, the ferroelectric material in the FeFET can be brought into two different polarization states by means of electric charges, and switching requires very little energy. Data retention measurements performed at 125ºC during a thousand hours proved the longevity of the saturated memory state, the device remaining operational at temperatures as high as 185°C. Talking about being cost-competitive, the new memory should enable significant cost-savings according to Mikolajiick, since it cuts both on process and material costs and it also scales down nicely beyond any other type of memory so far, without any exotic 3D design intervention. The researcher reckons that such a memory may turn to be half cheaper than competing technologies. In a first batch produced at the Frauhofer IPMS Center for Nanoelectronic Technologies in collaboration with GlobalFoundries, the researchers have tried various cell arrangements to test different array architectures, mostly variation of NOR-type architectures. Next on the lab’s roadmap is to further reduce the operating voltage, bringing it down as low as possible to reduce the sizing and footprint of peripheral driving circuitry and also to make the devices run faster. NaMLab acquired the IP before Qimonda went bankrupt and has now applied for patents on FeRAM memory using FE-HfO2, but Mikolajiick declined to comment on future licensing strategies. Memory trends: a look ahead By Janine Love As 2014 was winding down, there was still a lot of talk about 3D memory, mobile memory, high-performance memory, and “next-gen” memory. So what trends and challenges will make the most noise in 2015? EE Times recently spoke with Jennie Grosslight, the memory test product manager at Keysight Technologies, about what she thinks will be the prevailing memory trends in 2015. As the memory test product manager, Grosslight is responsible for Keysight’s logic analysis and compliance test tools for memory applications. With 25 years of experience and an electrical engineering degree from the University of Colorado, she has worked as an R&D engineer, technical marketing engineer, and product marketing engineer. She has been focused on helping engineers analyze and validate memory systems for the past 11 years. What can we expect for memory in 2015? What are the trends you see? Price, power, and performance will continue to be the driving features of memory deployment. Both DDR4 and LPDDR4 offer impressive performance improvements and power savings. DDR4 will see broader deployment to replace DDR3 in servers and begin “trickle-down” deployment in high-end desktop workstations. This will improve cloud performance and save power. LPDDR4-based products will hit the market, and mobile memory will take over as the technology driver for the memory industry overall. As DDR4 and LPDDR4 DRAM sales increase, prices will decrease, driving even more design starts with these technologies. Finally, universal flash storage-based products will be formally introduced, laying the foundation for a quantum jump in mobile systems performance and price/performance. If you could tell engineers one thing about memory test, what would it be? DDR memory is at the heart of today’s cloud computing servers - most of them having at least 24 DIMMs across four channels. With some data centres reporting that DDR memory is the second-highest failure they experience, the need for robust testing of designs continues to grow. To increase margin and overall performance and create a reliable and robust system, close attention to physical layer and functional testing, characterization, and debug to validate that the system is operating within JEDEC specifications is a critical step. What has surprised you most about memory development over the past 3-5 years? In the industry, the biggest surprise has been the emergence of the “Memory Wall” as a fundamental issue, its impact on computing architectures, and the incredible burst of innovation it has stimulated. For the past 10 years, memory has progressed along an evolutionary path, with DDR succeeding SDR, then DDR2, DDR3, and DDR4. Now, everything from 3D silicon cubes to distributed memory architectures and completely new signalling methods are in development with some already deployed. Every few months a new possibility seems to emerge for consideration. It’s the most interesting time to be involved in memory in the last 20 years. Along this evolutionary path, lower power and increased data rates in LPDDR technologies for mobile applications continues to push the limits. The LPDDR specification in mobile applications now has the performance of DDR technologies in computing. From a memory test perspective, it is surprising to see that there are servers being shipped without testing to specifications. Simply designing to recommended guidelines and running software tests to validate system operation doesn’t validate that the system is operating within specifications. When systems violate functional or parametric specifications for DDR/ LPDDR memory, the system may not fail with each violation. However, as the number of violations increase, so does the rate of memory failures. The degree of difficulty in testing different DDR or LPDDR memory is highly dependent on the layout of the system under test and associated subsystem verification. To ensure this verification has occurred, data centres should consider requiring qualification reports. What are the major stoppers/technical hurdles for mobile memory? Storage? Reducing power consumption, total memory channel throughput, and signal density are the key requirements and hurdles. Interfaces need to get faster, wider, denser, or some combination of these to improve channel throughput. Packages need to pack more signals, and this increased signal density causes crosstalk effects. Traditional single-ended signalling beyond 3Gbit/s is very hard and power hungry. Very wide I/O using 3D silicon 28 Electronic Engineering Times Europe January 2015 www.electronics-eetimes.com


EETE JAN 2015
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