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Ultra-Miniature | High Reliability Quartz Crystals, Oscillators and Sensors Medical Defense and Aerospace Industrial UNSURPASSED QUALITY • H i g h e s t m e c h a n i c a l s h o c k s u r v i v a b i l i t y i n t h e i n d u s t r y • Military temperature range and beyond • Exceptional stability and precision • Ultra-low power consumption • Excellent long-term aging AS9100C ISO 9001:2008 CX4_GLASS_A CX16A CX18A CX9A CX11A CXOL_A STATEK CORPORATION 512 N. Main St., Orange, CA 92868 Tel. 714-639-7810 | Fax 714-997-1256 www.STATEK.com Jennie Grosslight, memory test product manager at Keysight Technologies. stacking is still exotic and expensive. Combining these multiplies the difficulties. A lot of experimentation, analysis, and advancements will be required to figure out the best way to overcome these challenges. Both DDR4 and LPDDR4 specifications include multiple enhancements in these areas. Are standards keeping up? Do we need more/fewer? The standards are keeping up for the most part. The main decision is what to standardize. Until now, the memory standards have been defined by the main application: desktop/server, graphics, mobile, and mass storage. The latest generations have borrowed heavily from each other to get the best performance. DDR4 has many features first done in GDDR5. LPDDR4 looks more like its desktop cousin, DDR4, than any previous generation. Going forward, standards may be classified more by the core technology, signalling system, and interconnect method than the traditional scheme. At some point, the parallel interface with DDR memory may not be able to keep up with the faster data rate. Serial lane interfaces could be considered to address that. Continued leadership and participation with JEDEC in writing and reviewing the memory standards by companies such as Keysight and their partners, such as FuturePlus Systems, will be a key part in ensuring the necessary test specifications are being created. How does testing differ for the various memory types? Are some memory types easier to test than others? Why? First, read and write data separation is a very challenging task in a memory designer’s work. At lower speeds, the phase difference between DQS and DQ is very obvious. Read is edge aligned with data, and write is centred aligned with data. At higher speeds, especially with LPDDR4, the phase difference between the read and write cycle is not obvious, and the preamble patterns are similar. Separating read and write cycles at higher speeds is more difficult. The use of different tools helps resolve this. For example, you can use a mixed-signal oscilloscope to trigger on the command using the command truth table. Second, probing continues to become more and more difficult in memory test. For functional testing, using a DIMM or SODIMM interposer provides the fastest and easiest access. Access for chip down or PoP package-on-package designs requires BGA rework or designing probing into the system. For physical layer testing, since JEDEC standards are defined at the balls of the DRAM, the size and location of the DRAM dictate the difficulty of probing access. How will memory test have to evolve to satisfy emerging trends? Memory test is constantly evolving. Physical layer and functional layer testing must continue to keep up with the JEDEC standards and data rates. Creation of standards and test specifications, along with the early design of hardware and software test www.electronics-eetimes.com Electronic Engineering Times Europe January 2015 29


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