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MEMORY & DATA STORAGE solutions to support them prior to new memory technologies being introduced into end products, will continue to be a priority, so customers always have the latest equipment for memory testing. One example is the U4154A/B. When it is combined with the FS2510 DDR4 DIMM interposer with FS1070 conversion from our channel partner FuturePlus Systems, we can capture the entire DDR4 bus; run functional compliance testing; follow the signal flow of address, command, and data; and view bus-level signal integrity with 5ps x 5mv resolution. Another test evolution is protocol analyzers. Protocol analyzers, such as the FuturePlus Systems DDR Detective, are targeted to look at only the address and command signals for functional memory specification parameters, power management and performance metrics, and give engineers real insight into these complicated protocols. For physical layer and parametric testing, the mixed-signal oscilloscope is used to decode command protocols for reliable read and write data testing. The test can be done automatically with DDR compliance test software and debug tools. What challenges will designers have to overcome in order to achieve success? As chipsets scale to smaller processes, designers will have to move from DDR or DDR2 to DDR3, 50MHz flash to 200MHz flash, and LPDDR2 to LPDDR3. The low-speed design capacitance and fanout concepts that have worked for years in flash memory will need to be updated to high-speed digital flows based on transmission lines and precise timing. Host testing may begin to be incorporated. Memory tests have always been device and not host (memory controller) focused. Host and channel specifications would be equally important and the need to characterize both would become necessary. Probing has always been a challenge and will continue to be. We are meeting that challenge with our new DDR4 BGA interposers like the W4633A DDR4 x4/x8 probing solution. DDR4 BGA interposer products are reliable and give a connection to the address/command/control and the DQ data signals to the U4154B. Similar new BGA and PoP probing technology that is proven to achieve data rates of 3.2Gbs is available for LPDDR4. Finally, if the interface eventually moves to serial to enable continued increases in speed, there are existing serial standards that can be adopted. High-speed designers will have to learn serial speed concepts like bit error rates, eye masks, and dual Dirac jitter/noise modelling. Test equipment that has been relied on for years will have to be upgraded and new measurement techniques applied. The concepts and products to support this are proven but will need to be mastered by a whole new group of designers. High reliability 8-Mb SRAMs achieve zero soft-error-rate Renesas has grown its Advanced Low-Power SRAM series, with the RMLV0816B and RMLV0808B devices, which have a density of 8 Mbits and are built with a fabrication process technology with a circuit linewidth of 110 nm. In the Advanced LP SRAM Series, which can achieve soft-error-free and latchup free operation, Renesas started mass production of 4 Mbit products fabricated in a fine feature size process with a 110 nm circuit line width in December 2013 and now has launched the 8 Mbit products in this series. The new devices are high-reliability products that achieve the same soft error rate as Renesas’ earlier products that were fabricated in a 150 nm process. They also achieve low-power operation with a standby current of maximum of 2 μA at 25°C, making them suitable for data storage in battery-backup devices. Measures to deal with soft errors due to alpha rays and neutrons in cosmic radiation are seen as critical; since Renesas has added a capacitor to the memory node in the cell of the Advanced LP SRAM devices, these devices have an extremely high resistance to soft errors. A common method for dealing with soft errors is to correct the errors that occur using an ECC (error correcting code) circuit embedded in the SRAM or user system. There are, however, limits to such techniques, such as not being able to correct multiple bit errors depending on the performance of the ECC itself. To deal with this issue, the Renesas Advanced LP SRAM adopts structural measures that suppress soft error occurrence itself. The results of system soft error testing in Renesas currently mass produced 150 nm process Advanced LP SRAM has shown that these devices are essentially soft error free. Additionally, the load transistors (p channel) in the SRAM cell are formed as polysilicon TFT devices, and since they are stacked in the upper layer of the n-channel MOS transistors that are formed on the silicon substrate, only nchannel transistors are formed on the underlying silicon substrate. As a result, there are no parasitic thyristor structures in the memory area and thus these devices have a structure in which latch-up cannot, in principle, occur. As a result of these design aspects, these products are SRAM devices with extremely high reliability compared to full CMOS type devices that have the ordinary memory cell structure. Renesas Advanced LP SRAM achieves an even more compact cell size by combining polysilicon TFT stacking technology with stacked transistor technology. For example, the cell size in Renesas 110 nm Advanced LP SRAM is comparable to that in a full CMOS type SRAM fabricated in a 65 nm process. 16 Mbit products fabricated in the 110 nm process will follow. Renesas www.renesas.eu 30 Electronic Engineering Times Europe January 2015 www.electronics-eetimes.com


EETE JAN 2015
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