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Fig. 5: Using combinational gates for clock gating. Use of combinational logic at CDC Path In an ideal situation, there should be no combinational logic present at the CDC Interface. If such logic is present it may lead to a glitch. Also the glitch may get sampled in the destination domain and may lead to erroneous behaviour. Here again designer needs to review all the paths at the interface. We may waive the structure shown in figure 6 if all the other inputs to this combo logic are static when used. Such structures can easily be caught with any CDC tool or in gls. Fig. 6: Combinational logic at CDC Path. Glitch at converging paths through an analogue block Referring to figure 7, we have two inputs A and B which are combined through an “and” gate and fed to analogue IP. There is also another “and” gate which has B and the output of an analogue IP as inputs. The output of the second “and” gate is fed back to the analogue IP. Consider a case where B toggles and A = 1 we may observe glitches at the output of the second “and” gate. This kind of design which is purely combinational (with some hard macros) is always glitch prone. The glitch may get sampled in the design and may lead to unexpected behaviour. Such cases need the attention of designer and needs to be fixed in design. It is very important to make our design free of any clock or data glitches to ensure correct functioning of the design. There are cases where such issues have not only caused functional failure but increased execution cycle time by adding some extra debug time and effort. Hence it is very important for a designer to take care of such issues at very early stage of design once flagged by tool or gls. Call for R&D Proposals for Public end-user Driven Technology Innovation (PDTI) Open: Jan. 15, 2015 Deadline: Feb. 28, 2015 at 17:00 (Brussels time) This competitive call for PDTI R&D proposals is related to the EU-funded Seventh Framework Programme (FP7) project ECHORD++ (European Clearing House for Open Robotics Development Plus Plus, Grant Agreement Number 601116). R&D consortia with partners established in an EU Member State or FP7 Associated State having comprehensive expertise in the development of advanced robotics technology are asked to submit experiment proposals, written in English only. The PDTI activities will take place in two scenarios, Healthcare and Urban Robotics. The indicative funding for the PDTI activities amounts to 2.4 Mio. € in total. Please note that the Seventh Framework Programme only offers part-funding of research activities. More information and the full call documents, including the guide for applicants and an electronic submission system, can be found on the web site http://www.echord.eu For further questions, please contact us via info@echord.eu Fig. 7: Glitch at converging paths through an analog block. www.electronics-eetimes.com Electronic Engineering Times Europe January 2015 33


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