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Fig. 3: LTPoE++ PD controller uses external MOSFET for increased power efficiency. sor has the additional benefit of protecting t he PSE controller from transients on the VEE supply. Linear’s PSE controllers also have an 80V abs max rating on all analog pins to provide native protection against transients. Reduced power dissipation Linear Technology’s fourth generation PSE and PD controllers support fully compliant IEEE 802.3at operation in addition to LTPoE++ power levels of up to 90W , while minimizing heat dissipation through the use of low RDS(ON) external MOSFETs and 0.25Ω sense resistors. This is important in high power systems where thermal design and power loss can be extremely costly, as well as in power-limited applications where the application needs to maximize the delivered power to operate within the application’s power budget. PSE and PD controllers with integrated MOSFETs have higher RDS(ON) characteristics, making thermal design more difficult as the heat is dissipated inside the device. Damage to a single port can bring down the whole chip. The LT4275 as shown in figure 3 is the only PD controller on the market that controls an external MOSFET to drastically reduce overall PD heat dissipation and maximize power efficiency, which is especially important at higher power levels. This novel approach allows users to size the MOSFET to meet the application’s exact heating and efficiency requirements, enabling the use of low RDS(ON) MOSFETs on the order of 30mΩ. The LT4275 can support any power level up to 90W. A single TVS and 100V abs max port pin provides more than enough protection against cable discharge events. The LT4275 operates over a wide -40°C to 125°C temperature range and is equipped with overtemperature protection that protects the device during momentary overload conditions. With this much protection, it’s easy to see how rugged applications can benefit. How LTPoE++ works LTPoE++ uses a 3-event classification scheme to provide mutual identi¬fication handshaking between the PSE and PD while maintaining backward compatibility with the IEEE 802.3at standard. The LTPoE++ PSE determines if a PD is a Type 1 (PoE), Type 2 (PoE+), or LTPoE++ device by the PD response to the 3-event classification scheme. The LTPoE++ PSE uses the 3-event classification scheme result to update the ICUT and ILIM thresholds. The PSE uses the ICUT threshold to police the PD current consumption. ILIM is used as a hard current limit to protect the PSE power supply during serious current faults. On the other end, the LTPoE++ PD uses the number of classification events it receives to determine whether it is connected to a Type 1, Type 2, or LTPoE++ PSE. If the LTPoE++ PSE measures the PD’s 1st classification event current as Class 0, Class 1, Class 2, or Class 3, the LTPoE++ PSE will proceed to power on the port as a Type 1 device. Otherwise if Class 4 is identified in the 1st classification event, the LTPoE++ PSE will continue with a 2nd classification event, as defined in the PoE+ specification. This informs the PD that it is connected to either a Type 2 or LTPoE++ PSE. The absence of the 2nd classification event indicates the PD is connected to a Type 1 PSE that is limited to Type 1 power. The Type 2 PD physical layer classification is defined by IEEE as two consecutive Class 4 results. An LTPoE++ PD must also display two consecutive Class 4 results in the 1st and 2nd classification events, making an LTPoE++ PD appear as a Type 2 PD to a Type 2 PSE. The LTPoE++ PSE will move on to the 3rd classification event after valid Class 4 measurements in the 1st and 2nd classification events. After two successful Class 4 measurements, a 3rd classification event is performed. The 3rd classifica¬tion event must switch to a class other than Class 4 to recognize the PD as LTPoE++ capable. A PD that maintains Class 4 during the 3rd classification event is considered by the LTPoE++ PSE to be a Type 2 PD. The IEEE 802.3at standard requires compliant Type 2 PDs to repeat Class 4 responses for all class events. The 3rd classification event informs the LTPoE++ PD that it is connected to an LTPoE++ PSE. Table 1 shows the class events permutations for the various PD power levels. Table 1: Class events permutations for the various PD power levels. www.electronics-eetimes.com Electronic Engineering Times Europe January 2015 35


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