The Newest Products for Your Newest Designs® open source hardware one engineer whose company is evaluating RISC-V and asked to remain anonymous. For more risk averse companies, it could take up to three years, he said. In a sign of the breadth of interest in RISC-V, Oracle, who hosted the workshop in a theatre at its headquarters here, had six engineers signed up to attend the event including the vice president of Oracle Labs. Eight engineers signed up from AMD, the most from any one place except UC Berkeley which gave birth to the initiative in August 2014. Other attendees came from companies including ARM, Ceva, eASIC, Lattice, Huawei, IBM and Nvidia. Google, HPE provide soft support At the workshop, software experts from Google and Hewlett- Packard Enterprise (HPE) described work porting to RISC-V firmware stacks they are trying to establish as industry standards. A Google engineer said the company has its Coreboot firmware already embedded in Chromebooks and Android-based TVs now running on RISC-V. He also called for help porting to RISC-V Google’s Go programming language, a project a threeperson www.electronics-eetimes.com Electronic Engineering Times Europe January 2016 9 Go Widest_UK_93x277.indd 1 12/22/15 10:37 AM team at Google has already started. HPE has cobbled together a rough port of the UEFI firmware used in x86 PCs and servers. RISC-V lacks power management, trusted mode and systems management specifications, said Abner Chang, an HPE software engineer working on the UEFI port. Microsoft also needs to fill in key pieces of the UEFI port, he added. Chang made a special plea for a management mode to enable the free core to achieve its full potential. “RISC-V is not just for embedded systems, we can bring it to PCs and servers,” he said. Another HPE engineer reported on a breakout group on defining the RISC-V memory model. “Memory subsystems are generally getting more complex…the feeling was there’s a lot of work to be done in this space,” he said, noting the potential to borrow many concepts established by x86 and ARM chips. A separate security group parsed out a wide range of topics RISC-V could address. The effort has already attracted attention and support from both the U.S. and India governments for national security projects. Draper Labs is developing a RISC-V chip using metadata to tag memory addresses with security policies, a concept developed in a secure computing program sponsored by DARPA last year. In India, the Modi government has approved a budget that includes funding for a national microprocessor development project. Work could start as early as March when funding starts to flow to the effort that aims to create a family of RISC-V-based processors that would be available for military systems as well as commercial users in India. A handful of papers presented projects using RISC-V as an embedded core in an FPGA that acts as an accelerator for various applications. For example, former Microsoft researcher Jan Gray described an FPGA using 400 RISC-V cores delivering nearly 100,000 Mips. Gray’s design, which he was able to boot on Christmas Eve, uses a novel network-on-chip with a compact router making it easier to place and communicate with cores in a large array. “This router will change the way people design large FPGAs,” he claimed of the design he has yet to complete and aims to license.
EETE JAN 2016
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