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EETE JULAUG 2012

NEWS & TECHNOLOGY CEA-LETI ANNUAL REVIEW On the photonics roadmap: chip-to-chip and intra-chip interconnects By Julien Happich tHe cea-leti annual review that took place late June was an opportunity to catch up with the state-of-the-art in microsys- tems and microelectronics. among the many lectures running in parallel, my bet was that a whole afternoon session on photonics would fill-up my curiosity on the topic. The different presenters all acknowledged that copper alone would not suffice to match the speed and data density required Fig. 1: A package acting as the optical layer, with integrated by future generations of consumer devices, with data streams mirrors receiving or transmitting the signal from mounted expected in the teraFlOPS range (1000 Giga Floating Opera- VCSELs and photodiode arrays. tions per Second). the general view was that the future of high- bandwidth chip interconnection lays in photonics, at different component levels. Dr. H. Yonekura from Shinko electric industries disclosed an optical connection via a polymer waveguide integrated into the PcB layout of multi-chip modules. Hence the package would also act as the optical layer, with integrated mirrors receiving the signal from mounted vcSels (vertical-cavity surface-emitting lasers) or transmitting it to photodiode arrays – see figure 1. The company tested a transmitter module at over 10Gbps with little signal degradation in the waveguide, stated Yonekura. a receiv- er module was also tested to 10Gbps/channel. Shinko electric industries has also prototyped a 10cm2 electrical and optical multi-chip module bearing several optical channels with the Fig. 2: Interlayer couplers consisting of a tapered mode waveguide layer buried into the PcB both in linear and curved transformer, a grating, and etched waveguides each patterns to bypass the electrical devices’ mounting ports. this terminated by mirror couplers. laminate is currently in trial production whilst the company col- lects information about the next generation of packages and is in talk with optical interconnection industry players. Kotura’s ceO & President, Jean-louis Malinge, presented a wavelength division multiplexing (wDM) approach to optical interconnects. already a recognized provider of silicon opto- electronic integrated circuits, the company is shipping variable optical attenuators (vOas) and wDMs supporting 100Gb/s (4 wavelengths x25Gb/s). Kotura’s technology platform supports flip-chip bonding of lasers for transceivers and its WDM solu- tions are scalable, meaning they could achieve 40 wavelengths x25Gb/s to enable data transfers of 1 Terabit on a single fiber, boasted Malinge. recently, the company has demonstrated a wDM receiver measuring only 16x11.5mm, with integrated Fig. 3: Moving the optical link deeper inside the processing chain. Germanium-based detectors only 3mm wide directly coupled to the silicon waveguides through a tapered section. it has also developed Ge photodiodes and micro-scale modulators to be embedded into the silicon dies where the multiplexers and waveguides are etched. For chip to chip optical interconnects, Malinge proposed an interesting solution, interlayer couplers that could be used in 3D module architectures – see figure 2. Fig. 4: Integrated electrical and optical interconnects on the the interlayer couplers consist of a tapered mode transformer, chip carrier and the board. a grating, and etched waveguides each terminated by mirror cards and ultimately into chips – see figure 3. Currently, optical couplers. connections are mostly used at the board’s edge. Moving the Dr. Bert-Jan Offrein, manager of photonics at IBM’s optical signal chain deeper means additional assembly efforts Zurich research lab is also a proponent of silicon photonics are required by the many optical components (transceivers) and for optical interconnects in computing applications. according high-precision assembly steps with all the reliability and cost to Offrein, we must move the optical link deeper inside the pro- issues that go with them. Here, photonics chips could combine cessing chain to increase the communication bandwidth at all the modulators, drivers, detectors, amplifiers, WDM filters and levels of computing systems, from inter-rack, to backplane, to cMOS electronics on one die. though, the chip-level assembly 10 Electronic Engineering Times Europe July/August 2012 www.electronics-eetimes.com


EETE JULAUG 2012
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