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EETE JULAUG 2012

NEWS & TECHNOLOGY CEA-LETI ANNUAL REVIEW of silicon photonics dies is not yet available and today’s photon- ics solutions need to be packaged into a transceiver housing for later assembly on boards. On iBM’s roadmap is the assembly of silicon photonics chips into the processor package, directly next to the processor chip. this approach would provide a much higher bandwidth density while simplifying the assembly process. the solution to interconnect the optical signals would be to build all the chip- level functions (cMOS logic and Si photonics) with integrated electrical and optical interconnects (both on the chip carrier and the board as shown in figure 4). This integration would allow one-step mating of all electrical and optical connections. this also means that carrier and board-level waveguides must be embedded into the substrates to distribute the optical signals. the FP7 project FireFlY started at the end of last year goes into that direction, looking at 3D nano-structured materials and components for the efficient guiding of light. IBM has already demonstrated ultra-high density (62.5mm channel pitch) wave- guides on top of PcBs and optical couplings between poly- mer waveguides and silicon photonics through the use of 45º mirrors and low loss (0.4dB) lateral lenses with good assembly Fig. 5: Large double-sided photonics interposers capable of tolerances (20mm lateral alignment for 1dB additional loss and interconnecting multiple dies. 100mm lens-to-lens distance tolerance for 1dB additional loss). Further in the future, Offrein would like to see a photonics layer sitting on top of stacked memory and logic dies, acting as an on-chip optical network capable of connecting various cores but also able to route the data traffic. in his presentation on 3D integration and silicon photonics, head of design programs and research director at cea-leti Dr. ahmed Jerraya emphasized that while 3D interconnects can increase bandwidth in a single chip, off-chip I/Os will soon be the bottleneck, calling for chip-to-chip but also on-chip (silicon board) Si-photonics to the rescue. this in order to reach data transfers in the 1tFlOP/s range at acceptable power levels. “Data transfer density and energy efficiency in Watts consumed per GFlOPs must be increased by at least a factor of 50 if we are to achieve the objective of 1tFlOP/w by 2016”, said Jer- raya. whereas electrical interconnects hit an i/O density limit, silicon photonics could still be efficient for distances less than a few centimetres as commonly found on Socs, explained the Fig. 6: A photonics die linking to logic through copper pillars researcher. this could be achieved through the use of large after opto-electrical signal conversion. double-sided photonics interposers capable of interconnecting multiple dies. Such interposers could be developed indepen- dently (as for memories and processors) and should be driven by ic design to minimise costs and power consumption – see figure 5. Maurizio Zuffada, the spokesperson for STMicroelectronics’ research on the topic, described Si photonics as a fundamen- tal technology to the company’s process roadmap. in fact, in partnership with luxtera, St has already started development of its first generation of photonics devices on 300mm Si wafers. The first results are expected for mid-Q4 of 2012 with full characterization before the end of the year. Zuffada also hinted at a hybrid solution with a photonics die linking the i/Os to logic through copper pillars after opto-electrical signal conversion – see figure 6. The first generation devices will target 25Gbps/link Fig. 7: In direct wafer bonding, InP dies are bonded on a with bandwidths over 100Gbps on chips smaller than 160mm3. CMOS wafer before substrate removal. Head of the cMOS Photonics lab at cea-leti, Sylvie Menezo discussed the need for integration of both passive and ics as crafted and characterized in the lab. to solve the chip active optical functions, including light emission such as laser interconnect issue, Fedeli proposed a direct wafer integration sources and e/O or O/e conversion through modulators and whereby a photonics inP wafer would be bonded to an elec- photodetectors. this view was comforted by her colleague from tronic SOi wafer, meaning again that such a 3D optical integra- the leti silicon platform, Jean-Marc Fedeli who unveiled the tion would not depend on the specific node used to produce various building blocks of what could be tomorrow’s photon- the electronic wafer – see figure 7. 12 Electronic Engineering Times Europe July/August 2012 www.electronics-eetimes.com


EETE JULAUG 2012
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