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EETE JULAUG 2012

DESIGN & PRODUCTS PROGRammablE lOGIC Developing a 200Gbit/s line card with 22nm FPGAs By Denny Scharf Two key DevelopmenTS are shaking up the FpGA world: the advent of 22nm programmable devices and the availability of devices strongly targeted towards specific markets through the use of hardened IP. These developments are reflected in a new generation of FpGA devices that use Intel’s 22nm process and a collection of hard Ip directed at target markets. The most obvious benefit of the 22nm technology is the ad- vantage that comes with any advance to a new process node: higher density with lower cost per logic function); higher perfor- mance; and lower power consumption per logic function. In addition to these familiar benefits, this 22nm Intel pro- cess brings its radically new transistor design – the Tri-Gate or “FinFET”. In this transistor, the three-dimensional gate-structure surrounds the channel, resulting in greater control than is pos- The first Speedster22i device - HD1000, based on a sible in a conventional planar transistor. A key consequence conventional programmable fabric with a carefully balanced of this is the ability to turn the transistor off more completely high-performance clock network than is possible with a conventional planar transistor due to the greater gate-to-channel surface area. Static power consumption mable fabric with a carefully balanced high-performance clock (i.e. leakage) derives from the failure to incompletely turn tran- network. Available as an engineering sample in Q4 2012, it has sistors off, and has evolved over the years into an escalating 700,000 look-up tables (LUTs), 86Mbits of embedded RAM and nightmare - devices burning power even when they’re not doing 756 Multiply-accumulate blocks. For communications applica- anything. now the problem can be minimized. tions there are 64 SerDes transceiver lanes (from 1 to 12.75 Despite the many benefits of FPGAs over ASICs with im- Gbit/s) with two HardIP 100GE MACs that are also configurable proved time to market, lower total cost of ownership and field as six 40GE or twenty-four 10GE links, as well as two HardIP reprogrammability, they still suffer from a “Swiss army knife” 100Gbit/s Interlaken interfaces, two HardIP PCI Express Gen 3 effect – adequately addressing a wide range of applications, interfaces and six HardIP DDR3 72bit 2.133Gbit/s controllers. but excelling in none. By directly focusing on a defined group of It is important to note that any unused HardIp block is fully target markets with complex hard Ip blocks integrated onto the bypassable so that the associated Ios or SerDes lanes are devices using standard-cell ASIC technology, certain applica- usable in any case. A PCI-Express-pluggable development plat- tions are the clear beneficiaries. form will be available at the same time as samples. These hardened Ip blocks include 100G/40G/10G ethernet MACs, Interlaken, PCI Express, and DDR3 memory controllers. Bandwidth is key These functions are traditionally implemented using the FpGA’s Bandwidth is a key requirement for the target markets. The programmable fabric – a waste of precious core resources, Speedster22i devices deliver that bandwidth in two forms – Io- which should be reserved for functions unique to the user, not based and transceiver-based. programmable Ios developed for functions that are standard. Hardening these blocks pro- by Intel’s partners conform to the LVCMOS, HSTL, SSTL, and vides huge benefits for designs that use them, from reduced LVDS standards, among others, and are especially powerful in design-time with no need to close timing on these blocks as they already work at the required performance level) to reduced power consumption as the ASIC designs are inherently superior in energy efficiency with no programmability overhead). This ap- proach also provides increased performance with no program- mability overhead and a reduced area/cost tradeoff. As a final boost there is no need to license the Ip. Clearly, applications using all the embedded blocks benefit the most from these focused Ip blocks. But even applications using none of these blocks still benefit from the 22nm FinFET process. Standard functions that are functionally indistinguish- able from one implementation to the next belong in hardened (ASIC) form. Proprietary functions (unique to the implementa- tion) belong in a programmable fabric. The first Speedster22i device, the HD1000, is based on a conventional program- Dr Denny Scharf is strategic marketing manager for Achronix Fig. 1: All-digital 12.75 Gbit/s transceiver. Semiconductor - www.achronix.com 38 Electronic Engineering Times Europe July/August 2012 www.electronics-eetimes.com


EETE JULAUG 2012
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