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DDR3 interface applica- market. In many tions, where 2.133Gbit/s cases, this data-rates are sup- abundance of ported. This means each memory obvi- 72bit DDR3 interface ates the need provides over 150Gbit/s for external of raw memory band- memory – pro- width, giving a total of viding further over 900Gbit/s if all six bandwidth and interfaces are used). power advan- Fig. 2: The eye diagram for the primary data bandwidth tages. 12.75Gbit/s SerDes port. is supplied by the sixty- The Hard Ip four SerDes transceivers, blocks used which operate over a data-rate range from 1 to 12.75Gbit/s. The in this illustra- Fig. 3: A 200Gbit/s linecard implemention all-digital architecture leads to strong superiority over anything tion, in aggre- with the HD1000. else available in the FPGA world. The critical metrics are jitter, gate, consume noise immunity, and power consumption – see figure 1. less than 1.5w. In an alternative implementation using FpGA Three development chip tapeouts have been completed on programmable fabric for these functions, at least 10W would the 22nm process, including the 12.75Gbit/s SerDes blocks. be consumed by these functions alone. Two key decisions are These show clear eye diagrams at 15Gbit/s, shown on figure 2, at the heart of Achronix’s Speedster22i product offering. First and worst case voltage and temperature from a transmit PRBS7 is the selection of Intel as a key partner – providing the most pattern measurement using a 1st order HpF Golden pll. The advanced semiconductor fabrication process in the world, as total jitter is 0.36UI peak-to-peak. well as IP, packaging, and engineering support. The second key to success has been the recognition that carefully-selected Ip A 200Gbit/s linecard blocks (appropriate to the target markets) bring huge advan- networking and optical transport are market segments that tages – cost, power consumption, and development time – to benefit enormously from this approach. They are power-sen- customers. sitive, and are heavy users of the functions that Achronix has chosen to harden – especially as the “convergence” trend con- tinues in the direction of universal packet-based communica- tion. ethernet is the clear winner for layer-two system-to-system links. Interlaken serves a similar function at the device-to-device (or board-to-board) level in chassis-based systems, such as core routers. DDR3 is the external memory of choice – especial- ly in view of its cost, capacity, and bandwidth advantages. Any application making use of these standard interfaces (and per- haps PCI Express also) will benefit from the use of the device. Figure 3 illustrates such an application – the 200G linecard. The dual CFP modules provide the ports to the outside world, each supporting a single 100G ethernet stream. The cor- responding system-side interface is represented by the dual Interlaken blocks – like Ethernet, a packet-based protocol, ideal for supporting multiple distinct channels or flows. These flows represent differing sources, destinations, and traffic types - and must be differentiated by the system in order to provide the appropriate quality of service to all traffic. The six DDR3 modules shown serve as packet buffers, storing traffic until the scheduling algorithm directs transmission. These functions are hard-wired on the die leaving all 700,000 LUTs for implementa- tion of the traffic-management algorithms. For this reason, an enormous amount of logic and memory is available in the FpGA fabric for implementing the user’s unique features and tech- nologies. Neither resources nor power are wasted on standard, undifferentiating blocks such as Ethernet or DDR3. Linecard power, in particular, is often required to meet a maximum level (eg, 200-300W), so that wasted Watts are certainly to be avoided. Another key point to note is the balance of data-path and memory bandwidth. Data-path flow is left-to-right (the Receive direction) and right-to-left (the Transmit direction). All such traffic is directed temporarily to (and from) the DDR3 modules. Thus the bandwidths are not independent, and must be bal- anced. A further boost to memory capacity is provided by the 86Mbits of on-device RAM – more than any other FPGA on the www.electronics-eetimes.com Electronic Engineering Times Europe July/August 2012 39


EETE JULAUG 2012
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