040-043_EETE-VF

EETE JULAUG 2012

DESIGN & PRODUCTS PROGRammablE lOGIC Expanding system control with PLDs and low overhead serial buses By Peter J. Stinson develoPing the architecture for a complicated system, the system control aspect of the design rarely gets the lion’s share of attention from architects and designers. in the best case, system control is the design’s second priority. in the worst case, it is forgotten about until the late stages of the design, when there is very little space on the board to accommodate the function, and very little time to re-architect the design to handle it. the designer traditionally has a few options in order to solve these problems: bribe the software designer to somehow put some of the control in software; scatter small Plds all over the board and suffer the wrath of layout for board space and routing congestion; or, sacrifice functionality in the name of schedule. Fig. 1: Typical I2C setup. none of these options are attractive. What is needed is an ap- proach that minimizes board space and routing while continuing driving data to the peripherals and the MiSo (master input, to minimize microprocessor cycle consumption and maintaining slave output) is responsible for driving data to the master. con- the desired functionality. trol for the bus is provided by a clock (SclK) and a slave-select cPlds and small FPgas are very often the solutions of (SS), both of which are driven by the master. While this arrange- choice for these situations. using cPlds and FPgas, a design- ment eliminates the need for arbitration, it does require more er can sacrifice centralized monitoring and control in favor of signaling – see figure 2. control that is more localized and distributed. creating a com- today there are relatively few restrictions with respect to the munication path that minimizes connections between a central use of either serial bus. as of 2006, nXP (formerly Phillips) no processor and distributed Plds comes closest to an ideal longer requires licensing feeds to implement the i2c protocol. it solution. luckily, low-overhead communications paths exist in should be noted, though, that fees are still required to obtain i2c the Serial Peripheral interface (SPi) standard that was originally slave addresses. however, for applications where the peripheral developed by Motorola, and the inter-integrated circuit (i2c) is not communicating with the outside world, this is not nec- standard originally developed by Phillips. these standards are essary. SPi, on the other hand, is a de facto standard with no not designed to provide the blazing throughputs required by formal documentation. however, the standard has been imple- most data paths, but they serve well in monitoring and control mented on a number of different embedded processors, show- applications where latency is not nearly as important. combin- ing that its de facto status has not hindered its acceptance. the ing the flexibility of FPGAs and CPLDs with these low overhead low overhead of both i2c and SPi have made both standards buses gives the system designer a tremendous amount of widely accepted and integrated into both microcontrollers and system control while minimizing the footprint required. peripherals. Low speed serial buses System monitor and control Physically and electrically, SPi and i2c are low overhead bus Monitoring and control on a single-board application is relatively standards that generally are very easy to understand from a straightforward. resets, interrupt lines and select lines are con- board implementation perspective. i2c only takes two signals trolled directly via a microcontroller or localized Pld. however, to implement: Sda (the data line) and ScK (the clock line). the where control needs to be centralized in a multi-board system, lines are open-drain and require pull-up termination. these lines then there is value in keeping the connections to a minimum. can be dropped across multiple masters and slaves, as seen in figure 1. The only additional requirement for the circuit is the inclusion of the appropriate amount of pull up termination to deal with the capacitance on the line. the problem with mul- tiple masters on a two-wire bus is the need to apply arbitration on the bus in order to deal with message collisions. But with a simple dedicated bus structure with one master, this problem can be avoided altogether. SPi is a 4-wire serial bus that eliminates the need for arbitra- tion by only allowing for a single master on the bus. Further- more, there are two data pins and neither is truly bidirectional. the MoSi (master output, slave input) line is responsible for Peter J. Stinson is Marketing Manager for north america and Fig. 2: Typical three slave SPI bus. europe for lattice Semiconductor - www.latticesemi.com 40 Electronic Engineering Times Europe July/August 2012 www.electronics-eetimes.com


EETE JULAUG 2012
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