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this is accomplished by using a low overhead serial bus to communicate to a PLD, as seen in figure 3. the next level of detail needed is a protocol that would require a command and addressing scheme in the data stream going from the microcontroller to the external Pld. For a SPi- based implementation, there is not much to worry about. SPi does not require anything in the datastream for addressing, as the SS and SclK signals provide the control addressing in the protocol. therefore, the user has control over the whole payload of the data transmission. the i2c implementation for an external Pld is a little more Fig. 4: Remote fault logging. complex. The PLD first must identify that it is the device being addressed before driving data back onto the bus. this dif- a master design to access the memory. the second alternative ference illustrates the tradeoffs between the two serial bus is to use the PLD as both a master and a slave. The benefit architectures: the SPi architecture does not require a command of this approach is that there is one serial bus in the system interpreter to address a particular slave, but requires more pins and therefore the microcontroller can access the non-volatile than an i2c architecture. memory directly, as opposed to having the Pld interpret the command and pull information from the memory. however, Remote fault logging instead of having a simple slave design in the Pld, the design given the relatively low cost of external non-volatile memory must now deal with addressing and bus control. and the ease of interfacing to it via a serial bus like i2c or SPi, using external non-volatile memory in conjunction with a Pld Sensor and peripheral aggregation can offer the user a cost-effective way to manage remote fault the number of standard products with serial-based interfaces logging in a system. Figure 4 shows a typical system application grows every day. You can find serial interfaces on temperature using not only the io expansion capability highlighted previous- sensors, pressure sensors, a/d converters, digital potentiom- ly, but also shows how an external memory can be architected eters, real-time clocks and lcd controllers, to name a few. the into the system. key to understanding how these can be integrated into a design in this architecture, the Pld is primarily responsible for moni- is to understand which of these peripherals needs to be used in tor, control and communication back to the microcontroller. “real-time” and what “real-time” means. For instance, tem- however, it is also responsible for performing additional analysis perature is a relatively slow moving phenomenon in a system on monitor/control lines and logging fault information via a serial and could easily be monitored by a serial bus. an a/d converter bus talking to a non-volatile memory. Failures in voltage moni- used for current or voltage sensing may or may not be a “real toring, watchdog timers and other failing conditions on a PcB time” requirement, depending on what is being measured and can be architected to have the Pld write into the non-volatile how fast it needs to be detected. memory. typically, the states of other monitors in the system, once you have determined the priority of the peripherals such as temperature and voltages as well as the time are saved you can then decide to offload the processor’s responsibility after a fault is detected. for the lower priority peripherals by placing them behind a Pld, It should be noted that there is one significant implementa- as seen in figure 5. In the above example, the microcontroller tion requirement for such a system. if the Pld is a master for is responsible only for communicating with two peripherals as the external non-volatile memory, then decisions would have opposed to four. to be made specifically for control and addressing on the serial There is one other benefit to this type of arrangement. A buses. the decision is very easy for the use of a SPi bus; the sufficiently powerful PLD could also be responsible for pre- designer must implement a slave SPi design for communication processing of the data before being read by the microcontroller. with the microcontroller and a separate master SPi design for as an example, consider an application where there is an a/d access to the external memory. sampling voltage and current measurements from a three-phase For the i2c bus, the designer has a couple of choices. the first choice is to implement the design similar to the SPI require- ments, with one slave design talking to the microcontroller and Fig. 3: PLD as a Serial IO expander. www.electronics-eetimes.com Electronic Engineering Times Europe July/August 2012 41


EETE JULAUG 2012
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