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DESIGN & PRODUCTS PROGRammablE lOGIC electrical system and checking for faults. A PLD with sufficient dSP capability can perform rMS calculations, peak current analysis, phasor calculations and FFts in lieu of having it done in either a dSP or the microcontroller. the sample rate is now limited by the time that the Pld requires to collect samples and process the data. the microcontroller can then read from the complied data and spend more time performing the tasks required for control and reporting. designers should look at the trade-offs between microcontroller processing power, PLD processing, cost and space. Next step: integration given the usefulness of these serial buses when combined with small programmable logic devices, the next step would be to in- tegrate at least one, if not both, of the serial bus standards into Fig. 5: Sensor aggregation example. a Pld. this integration decreases the cost of a Pld solution as well as the power consumed. in addition, coding the serial also provides designers with a timer/counter block as well as bus interface no longer becomes an issue for the designer. the access to a small amount of user-accessible Flash memory designer only needs to deal with their application and the logic (uFM). aside from above mentioned solutions, serial buses required, as opposed to integrating an open core. the latest combined with PLDs can provide additional system benefits, CPLD offering from Lattice Semiconductor realizes this benefit. even if sometimes they come as an afterthought in the architec- the embedded functional block (eFB) found in the MachXo2 ture process. they are not a panacea for all ills, but their utility family contains pre-engineered solutions that can be used to in designs is well documented and there are numerous open- implement any of the system control functions described above. source cores and design ideas available to guide designers the MachXo2 device contains one SPi controller as well as two through different architectures in order to come to the optimal i2c controllers. all of the serial buses controllers can be con- solution. figured as either a master or a slave. In addition, the MachXO2 OpenCL emerges for FPGA high level design By nick Flaherty in the deBate aBout high level design, a new standard is erator blocks on an FPGA. It’s like a PC running with a floating emerging for FPga designers to use alongside vhdl, verilog point maths co-processor.” and System c to bridge the gap. oPencl started life at apple using opencl for the development can provide a speed up to handle the programming of multiple cores and has since of 35x in system performance over a CPU implementation at the been adopted by the Khronos organisation which also develops same time as reducing the design time by half, he says. “that’s the opengl series of graphics formats. While it can be seen the key thing with opencl, to be able to develop most of the as a desktop technology with support from companies such as system on the host processor in standard anSi c with a stan- intel, aMd and nvidia, it is also backed by embedded chip de- dard c compiler, then your opencl code, which is c with paral- signers such as texas instruments, Broadcom and cambridge lel extensions, gets put across to a device specific compiler for Silicon radio. the FPGA or GPU. That’s the reason it fits best into processor an increasing number of FPga designs are using multiple based systems,” said davis. cores, especially if those cores are dSP accelerator blocks. the other advantage is that this is essentially the same code, With the new generation of system on chip FPgas from altera says davis, but “you may have to tweak the kernel code for the and Xilinx that integrate hard macro arM cores, opencl is particular architecture. There are different memory architectures becoming an interesting high level design technique for a num- in a gPu and in an FPga but the fundamentals of the opera- ber of applications. opencl is particularly suited to streaming tions are the same, it’s about how you move the data around,” applications such as broadcast, military signal processing, high performance computing OpenCL future directions (hPc) and medical imaging applications, says For future developments, the opencl group is looking at opencl-hlM (high craig davis who is responsible for the roll out level Model), unifying the host and device execution environments through the of opencl across europe for altera. “it works language syntax. this would provide increased usability and broader optimiza- particularly well when you are developing your tion and address several of the issues raised by the FPga vendors. the group algorithm in c and instead of going to hdl you is also looking at the long term core roadmap, exploring enhanced memory and can stay in a c-like development environment execution model. at the same time it is exploring a version called Webcl to bring and improve your time to market,” he said. parallel computation to the Web through a JavaScript binding to opencl. then the “a typical application for opencl to be de- opencl-SPir (Standard Parallel intermediate representation) will explore tech- ployed is where you have a processing system niques to hide code for security applications and to provide a target back-end for on an x86 running the host programme with an alternative high-level languages. interface like Pci express linked to the accel- 42 Electronic Engineering Times Europe July/August 2012 www.electronics-eetimes.com


EETE JULAUG 2012
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