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he said. there is also a hidden advantage in debugging, he says. the same code can be run on an array of gPus and on an FPga, and if the same bugs appear you know they are in the code rather than in the compiler or quirks of the architecture. altera has already set up an early access pro- gramme with stand-alone opencl development tools for certain customers across europe, and the tools are set to be integrated into the Quartus development environ- ment early next year. Xilinx is keeping a close eye on the technology but doesn’t believe it is mature enough or portable enough between the different OpenCL allows C code with extensions for platforms. parallel operation to run on both a host CPU “i think there’s a renewed and an embedded array of cores in an FPGA. interest in high level design (hld) rather than eSl,” said tom Feist, senior director of marketing at Xilinx in oregon, just down the road from Khronos. “What has happened over time is that people tried it and found that it didn’t quite work. high level synthesis works for iP generation and algorithm development, but not for a system. You have to worry about interface syn- thesis. HDL works with a team that starts with a C specificationand turns that to RTL, but it’s not in a place today where there’s code on a processor and you can just push a button to get the design.” “One of the things that definitely needs to happen is better agreements on what data types to use and perhaps submit back to System c as synthesisable data types,” he said “But even at the source code level we need to tighten up the stan- dards. We all have the same optimisations for loops etc so ultimately it should be possible to optimise high level synthesis constraints like Synopsys did with timing constraint.” one argument is that a new design methodology isn’t necessary. “if you want to be successful in high level synthesis you have to embrace what the designers are already using such as c, c++ and System c, “ said dirk Seynhaeve, senior product marketing for high level synthesis at Xilinx. “So we are really agnostic. there are parallel threads on System c but we are also automatically generating parallel threads in our tools.” “We do look very closely at what’s going on with opencl and particularly active with Khronos,” he said. “unfortunately the portability of the code is something we still have to deliver on. it’s only between cPus and gPus and even there there’s only a small intersection. even aMd and nvidia say portability is a bit of a dream.” While version 1.2 of OpenCL was released last November, three years after the first full version was released, it wasn’t a big enough change, says Xilinx, particularly when it comes to moving the OpenCL code between different platforms. “We have very high hopes of the second version of the standard that would finally give an opening for FPgas to be added for portability but not for performance,” said Seynhaeve. even if there is portability between platforms the code will always have to be modi- fied to get the best performance. “You always have to do some kind of tuning to get the extra performance out of the platform. You can have a soft core processor as the host and create an array of other soft processors, we agree that this is one way of ac- celerating an algorithm,” he said. We certainly believe that until we get to opencl 2.0 the best embedded solution is an FPga with a cPu core and most of the market is c, c++ and Systemc based.” “opencl2.0 is not in the short term,” said Seynhaeve. “if you truly want to do full parallelism you need to fully utilise the processor. there’s manual vectorisation sup- port in OpenCL1.2 but it’s still going to be a manual process. Altera is not sanguine on the amount of work to be done. “There’s more work we are doing with different ways of moving data around and enhancing the specification for example with a stream- ing interface,” said davis. “if you have data driving a Pcie link or other interface like Ethernet it would be very good to extend the specification to handle that.” Xilinx is less enthusiastic. “the committees take a long time,” said Feist ”so our strategy is not to dictate a design flow but to automate it.” Withtools emerging for OpenCL in the FPGA design flow and early adopters already using it in key applica- tions, there is potential for this to emerge as a significant new way to quickly develop high performance parallel applications across multiple cores. www.electronics-eetimes.com Electronic Engineering Times Europe July/August 2012 43


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