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EETE JULAUG 2013

Company Announcement Generation 10 Portfolio from Altera Ultra high defi nition broadcast equipment, 400G Ethernet systems and computer data centres – all feast on vast quantities of data. Consuming and processing that level of data with any electronic system is diffi cult. You will need to be at the leading edge of technology, both with the architecture you use to process the data and the manufacturing process you use to generate the device. FPGAs have for many years been at this forefront of technology, Moore’s law has been kind to FPGAs - with the right process/ architecture design decisions you can reduce power, increase performance and reduce cost/ increase density at each generation. Each generation of FPGA captures more applications that previously would have had to be designed with ASICs, and opens a new market due to the performance, fl exibility, power or cost that couldn’t be reached with the older technology. There are three key aspects to consider when creating an ideal modern FPGA. • Leading-edge manufacturing processes technology • Investments in innovative architecture and IP • High-performance integration of processors with programmable fabric Advanced process technologies are key for next generation FPGAs. For example, a new 3D transistor technology known as Tri-Gate or FinFET transistor technology is a breakthrough change in process technology. It halves leakage current of transistors, which enables high performance or low power capabilities. Most process-technology foundry suppliers are in the early test chip stages of fi nFET. At the time of writing, Intel is the only manufacturer who has production quality products shipping using a 3D (Tri-gate) transistor technology. Customers looking and asking for performance improvements will not get this from 3D transistor technology alone, but they will also need a process shrink. The recently announced 14 nm Tri-Gate process from Intel provides this process technology. Altera’s future Stratix 10 FPGAs will be built using Intel’s 14 nm Tri-Gate process. Process is only part of the story; Altera is currently developing a new architecture which is capable of astonishing core speeds of up to 1 GHz. The enhancements to the digital signal processing (DSP) architecture delivers a dramatic improvement to DSP capability enabling over 10 TFLOPs of single precision fl oating point operations. Transceiver performance also gets a boost with the ability to run at up to 56 Gbps data rates. Within the Generation 10 portfolio Arria 10 FPGAs use a 20 nm planar transistor process to implement sixteen 28 Gbps transceivers for next-generation multi-100G optical interfaces. With enhanced signal conditioning techniques, such as adaptive decision feedback equalizers (DFE), and hardened forward error correction (FEC), high loss backplane applications can be addressed. Processor Integration FPGA integration of discrete components on a board has reduced the complexity and cost of many customer systems, but one of the most important changes has been the recent integration of an ARM-based hard processor sub-system (HPS). Altera Arria 10 SoCs offer enhanced dual core ARM Cortex™-A9 HPS, this is a boost for customers wanting tighter integration between CPU and FPGA fabric. The next generation HPS is shown in Figure 3. Figure 3: Second-Generation HPS Block with ARM Cortex-A9 Processor Next-Generation FPGAs and SoCs Are Coming Altera uses a tailored innovative approach to portfolio design, coupling new architectures to the latest process technology to bring together an exciting suite of FPGAs. It’s fair to say the Generation 10 portfolio will have the largest leap in capabilities that hardware architects and system designers are yet to see thus far in an FPGA. Visit www.altera.com for more information Figure 1: Tri-Gate Process Technology Figure 2: 28 Gbps Operation on 20 nm Process Technology from Altera


EETE JULAUG 2013
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