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EDA & DESIGN TOOLS Fig. 3: Collaborating, comparing and merging hardware building blocks in Altium Designer. All changes are subsequently only maintained incrementally. Since repeatedly saving the complete design as a new revision number takes up enormous volumes of data storage space, the system only saves the incremental changes. One potential source of design changes is a process referred to a “branching”. Branching allows the design team to explore “what-if” scenarios as a branch of the main line of development. Any authorized team member can establish a branch at any point in the main development line. If V1.0 is released, branching allows for minor fixes. Branching allows for these fixes, if appropriate, to be incorporated into subsequent product releases. Design teams using EDA tools with a fully integrated version control system experience many benefits, the first of which is a reduction in errors. Accountability and productivity improve because each engineer can view who is making changes in the design and see that engineer’s work. Each team member can then readily ask questions of that designer regarding that specific change. Further, because all team members can see each other’s work, productivity improves. After implementing an integrated VCS, documentation and reporting also improve. Each time a team member checks a file back in, he or she must add a comment. This facilitates project management, QA, and standards compliance to get products certified to current relevant industry standards. Further, with full graphic and onscreen visual comparisons between two different revisions, team members can view highlighted changes sideby side. Altium Designer answers the version control needs of hardware design teams. It delivers the only fully integrated EDA version control system. All design data are maintained in a single repository and the data remain fully synchronized. The system displays changes in up to four panels on screen. This advanced capability further highlights all changes in both the schematic and the PCB – see figure 3. All changes are also documented as text to enhance management oversight. Timing closure highlights the challenges of 45nm silicon design and below By Chi-Ping Hsu Inovation is the cornerstone of the semiconductor industry and has been responsible for massive changes in all parts of the industry, from design through fabrication, assembly and test. The foundational requirements of innovation in design are changing; they are expanding in scope. Point solutions that locally optimize a single design process by some metric, such as power, are more often than not proving to be a net disruption to design closure, rather than a benefit. The necessarily expanded scope of innovation, especially true for advanced node design, means that the most significant innovations will come from large organizations that are willing to make bold investments. We estimate that the EDA investment for the move to 20nm and 14nm FinFET to be in the $1B range. For the size of our industry, this is indeed a bold, albeit necessary, investment. We can regard the issue of timing signoff as a microcosm of the way in which innovation in EDA has changed and how it is evolving now and into the future. Cadence Design Systems has responded with the recent introduction of its Tempus Timing Signoff Solution, a new static and timing analysis closure tool that yields up to an order of magnitude faster than traditional timing analysis solutions. Although start-ups have developed new technologies that solve individual parts of the signoff problem, those innovations sometimes do not make it through to the implementation flows used by system-on-chip (SoC) engineering teams because they do not solve the overarching problems. Over the past decade and a half, the physics of nanometer technology have taken an increasingly firm grasp on the design process and created a much more complex situation for signoff. The shift from ASIC to SoC design that began in earnest at the start of this millennium accompanied a dramatic change in methodology and also the way in which innovative design technologies came to the market. Just 15 years ago, signoff for digital logic-dominated designs was relatively straightforward thanks to the use of widely accepted approximations. Gate delay strongly outweighed wire delay, which could be treated as practically negligible. Signoff was largely a matter of performing timing analysis based on the results provided by the ASIC vendor’s ‘golden’ gate-level simulator. Chi-Ping Hsu is Senior VP, Research and Development, Silicon Realization Group at Cadence Design Systems – www.cadence.com 20 Electronic Engineering Times Europe July/August 2013 www.electronics-eetimes.com


EETE JULAUG 2013
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